GNUBoot/coreboot-kgpe-d16
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Edward O'Callaghan 946bee1c34 superio/ite/it8728f: RAMstage PNP configuration component 
Provide devicetree.cb RAMstage configuration of this superio component.

Change-Id: I376d2fb6dafc301cbc437518012f8c43b0af4be2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5668
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-05-11 17:20:31 +02:00
..
arch SeaBIOS: Fix cpp use 2014-05-11 08:51:54 +02:00
console console: Fix UART selection prompt 2014-04-30 23:47:28 +02:00
cpu Replace SERIAL_CPU_INIT with PARALLEL_CPU_INIT 2014-05-10 11:27:25 +02:00
device Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
drivers Intel FSP: add a shared set of functions for the FSP 2014-05-09 21:35:56 +02:00
ec baytrail: Basic DPTF framework 2014-05-09 05:42:52 +02:00
include ramstage_cache: allow ramstage usage add valid helper 2014-05-10 06:31:45 +02:00
lib ramstage_cache: allow ramstage usage add valid helper 2014-05-10 06:31:45 +02:00
mainboard Replace SERIAL_CPU_INIT with PARALLEL_CPU_INIT 2014-05-10 11:27:25 +02:00
northbridge cougar_canyon2: Switch CPU/NB/SB to the shared FSP code 2014-05-09 21:36:12 +02:00
soc baytrail: cache reference code for S3 resume 2014-05-10 06:31:59 +02:00
southbridge cougar_canyon2: Switch CPU/NB/SB to the shared FSP code 2014-05-09 21:36:12 +02:00
superio superio/ite/it8728f: RAMstage PNP configuration component 2014-05-11 17:20:31 +02:00
vendorcode Declare get_write_protect_state() without ChromeOS 2014-05-08 16:25:30 +02:00
Kconfig Arch-level Kconfig menu cleanup 2014-05-10 14:32:26 +02:00