422bf6b472
Add a port of Auron_Paine based on upstream Auron and the Auron_Paine code originally from commit bd61dfd in Google branch firmware-paine-6301.58.B . Change-Id: I3a1faec3195a81bb3a6496b8bd610fc8a89e66aa Signed-off-by: Georg Wicherski <gwicherski@gmail.com> Reviewed-on: https://review.coreboot.org/11907 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
35 lines
1.1 KiB
C
35 lines
1.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef THERMAL_H
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#define THERMAL_H
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/* Control TDP Settings */
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#define CTL_TDP_SENSOR_ID 0 /* PECI */
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#define CTL_TDP_POWER_LIMIT 12 /* 12W */
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#define CTL_TDP_THRESHILD_NORMAL 0 /*Normal TDP Threshold*/
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#define CTL_TDP_THRESHOLD_OFF 85 /* Normal at 85C */
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#define CTL_TDP_THRESHOLD_ON 90 /* Limited at 90C */
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/* Temperature which OS will shutdown at */
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#define CRITICAL_TEMPERATURE 104
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/* Temperature which OS will throttle CPU */
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#define PASSIVE_TEMPERATURE 95
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/* Tj_max value for calculating PECI CPU temperature */
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#define MAX_TEMPERATURE 105
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#endif
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