bf72dcbd2f
Use CAPID0_A to provide information closer to reality. * Correctly advertise ECC support, max DIMM count and max capacity * CAPID0_A hasn't changed since SNB, but most EDS mark the bits as reserved even though they are still used by FSP. * Assume the same bits for Tiger Lake as for Ice Lake * Assume the same bits for Skylake as for Coffee Lake * Add CAPID0_A to Icelake headers The lastest complete documentation can be found in Document: 341078-002. Change-Id: I0d8fbb512fccbd99a6cfdacadc496d8266ae4cc7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
103 lines
2.6 KiB
C
103 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <cpu/x86/msr.h>
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#include <delay.h>
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#include <device/device.h>
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#include <device/pci_ops.h>
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#include <intelblocks/power_limit.h>
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#include <intelblocks/systemagent.h>
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#include <soc/cpu.h>
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#include <soc/iomap.h>
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#include <soc/msr.h>
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#include <soc/pci_devs.h>
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#include <soc/systemagent.h>
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#include "chip.h"
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bool soc_is_vtd_capable(void)
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{
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struct device *const root_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
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return root_dev &&
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!(pci_read_config32(root_dev, CAPID0_A) & VTD_DISABLE);
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}
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/*
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* SoC implementation
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*
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* Add all known fixed memory ranges for Host Controller/Memory
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* controller.
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*/
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void soc_add_fixed_mmio_resources(struct device *dev, int *index)
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{
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struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD);
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static const struct sa_mmio_descriptor soc_fixed_resources[] = {
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{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
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"PCIEXBAR" },
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{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
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{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
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{ EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
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{ GDXCBAR, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE, "GDXCBAR" },
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{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
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};
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const struct soc_intel_skylake_config *const config = config_of(dev);
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sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
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ARRAY_SIZE(soc_fixed_resources));
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if (!config->ignore_vtd && soc_is_vtd_capable()) {
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if (igd_dev && igd_dev->enabled)
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sa_add_fixed_mmio_resources(dev, index,
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&soc_gfxvt_mmio_descriptor, 1);
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sa_add_fixed_mmio_resources(dev, index,
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&soc_vtvc0_mmio_descriptor, 1);
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}
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}
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/*
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* SoC implementation
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*
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* Perform System Agent Initialization during Ramstage phase.
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*/
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void soc_systemagent_init(struct device *dev)
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{
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struct soc_power_limits_config *soc_config;
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config_t *config;
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/* Enable Power Aware Interrupt Routing */
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enable_power_aware_intr();
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/* Enable BIOS Reset CPL */
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enable_bios_reset_cpl();
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/* Configure turbo power limits 1ms after reset complete bit */
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mdelay(1);
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config = config_of_soc();
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soc_config = &config->power_limits_config;
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set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
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}
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int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base,
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uint64_t *prmrr_mask)
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{
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msr_t msr;
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msr = rdmsr(MSR_UNCORE_PRMRR_PHYS_BASE);
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*prmrr_base = (uint64_t) msr.hi << 32 | msr.lo;
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msr = rdmsr(MSR_UNCORE_PRMRR_PHYS_MASK);
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*prmrr_mask = (uint64_t) msr.hi << 32 | msr.lo;
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return 0;
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}
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uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)
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{
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switch (capid0_a_ddrsz) {
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case 1:
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return 8192;
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case 2:
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return 4096;
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case 3:
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return 2048;
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default:
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return 32768;
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}
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}
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