834b3ecd7c
This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file() to cbfs_map() and cbfs_load() respectively. This is supposed to be the start of a new, better organized CBFS API where the most common operations have the most simple and straight-forward names. Less commonly used variants of these operations (e.g. cbfs_ro_load() or cbfs_region_load()) can be introduced later. It seems unnecessary to keep carrying around "boot" in the names of most CBFS APIs if the vast majority of accesses go to the boot CBFS (instead, more unusual operations should have longer names that describe how they diverge from the common ones). cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly reap mappings when desired. A few new cbfs_unmap() calls are added to generic code where it makes sense, but it seems unnecessary to introduce this everywhere in platform or architecture specific code where the boot medium is known to be memory-mapped anyway. In fact, even for non-memory-mapped platforms, sometimes leaking a mapping to the CBFS cache is a much cleaner solution than jumping through hoops to provide some other storage for some long-lived file object, and it shouldn't be outright forbidden when it makes sense. Additionally, remove the type arguments from these function signatures. The goal is to eventually remove type arguments for lookup from the whole CBFS API. Filenames already uniquely identify CBFS files. The type field is just informational, and there should be APIs to allow callers to check it when desired, but it's not clear what we gain from forcing this as a parameter into every single CBFS access when the vast majority of the time it provides no additional value and is just clutter. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
123 lines
3.3 KiB
C
123 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <acpi/acpi.h>
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#include <bootstate.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <fsp/api.h>
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#include <fsp/util.h>
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#include <intelblocks/fast_spi.h>
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#include <soc/iomap.h>
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#include <soc/intel/common/vbt.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include <soc/fiamux.h>
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#include <spi-generic.h>
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#include <soc/hob_mem.h>
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static struct device_operations pci_domain_ops = {
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.read_resources = &pci_domain_read_resources,
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.set_resources = &pci_domain_set_resources,
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.scan_bus = &pci_domain_scan_bus,
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};
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static struct device_operations cpu_bus_ops = {
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.read_resources = noop_read_resources,
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.set_resources = noop_set_resources,
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.init = denverton_init_cpus,
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#if CONFIG(HAVE_ACPI_TABLES)
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.acpi_fill_ssdt = generate_cpu_entries,
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#endif
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};
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static void soc_enable_dev(struct device *dev)
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{
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_DOMAIN)
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dev->ops = &pci_domain_ops;
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else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
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dev->ops = &cpu_bus_ops;
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}
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static void soc_init(void *data)
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{
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fsp_silicon_init(false);
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soc_save_dimm_info();
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}
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static void soc_final(void *data) {}
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static void soc_silicon_init_params(FSPS_UPD *silupd)
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{
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size_t num;
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uint16_t supported_hsio_lanes;
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BL_HSIO_INFORMATION *hsio_config;
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BL_FIA_MUX_CONFIG_HOB *fiamux_hob_data = get_fiamux_hob_data();
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/* Configure FIA MUX PCD */
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supported_hsio_lanes =
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(uint16_t)fiamux_hob_data->FiaMuxConfig.SkuNumLanesAllowed;
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num = mainboard_get_hsio_config(&hsio_config);
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if (get_fiamux_hsio_info(supported_hsio_lanes, num, &hsio_config))
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die("HSIO Configuration is invalid, please correct it!");
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/* Check the requested FIA MUX Configuration */
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if (!(&hsio_config->FiaConfig)) {
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die("Requested FIA MUX Configuration is invalid,"
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" please correct it!");
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}
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/* Initialize PCIE Bifurcation & HSIO configuration */
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silupd->FspsConfig.PcdBifurcationPcie0 = hsio_config->PcieBifCtr[0];
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silupd->FspsConfig.PcdBifurcationPcie1 = hsio_config->PcieBifCtr[1];
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silupd->FspsConfig.PcdFiaMuxConfigRequestPtr =
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(uint32_t)&hsio_config->FiaConfig;
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}
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void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
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{
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const struct microcode *microcode_file;
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size_t microcode_len;
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microcode_file = cbfs_map("cpu_microcode_blob.bin", µcode_len);
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if ((microcode_file != NULL) && (microcode_len != 0)) {
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/* Update CPU Microcode patch base address/size */
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silupd->FspsConfig.PcdCpuMicrocodePatchBase =
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(uint32_t)microcode_file;
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silupd->FspsConfig.PcdCpuMicrocodePatchSize =
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(uint32_t)microcode_len;
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}
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soc_silicon_init_params(silupd);
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mainboard_silicon_init_params(silupd);
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}
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struct chip_operations soc_intel_denverton_ns_ops = {
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CHIP_NAME("Intel Denverton-NS SOC")
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.enable_dev = soc_enable_dev,
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.init = soc_init,
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.final = soc_final
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};
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struct pci_operations soc_pci_ops = {
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.set_subsystem = pci_dev_set_subsystem,
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};
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/*
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* spi_flash init() needs to run unconditionally on every boot (including
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* resume) to allow write protect to be disabled for eventlog and nvram
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* updates. This needs to be done as early as possible in ramstage. Thus, add a
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* callback for entry into BS_PRE_DEVICE.
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*/
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static void spi_flash_init_cb(void *unused)
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{
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fast_spi_init();
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}
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BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL);
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