Shelley Chen 9573c0ed3a soc/qualcomm/sc7280: Enable compression of SHRM ... The SHRM region needs to be 4 byte aligned, which make enabling compression slightly more complicated. We need to map it to cached memory before loading it and flushing to memory (in aligned chunks) then remapping the address space back to device memory before beginning execution of the SHRM region. Also, did some cleanup in this file based on comments in CB:49392. BUG=b:182963902 BRANCH=None TEST=Make sure we can still boot to kernel on herobrine Change-Id: Iaad8a8a02abe40bd01766d94ef0b61aac7671936 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>		2021-10-15 15:38:34 +00:00
..
amd	soc/amd/cezanne,picasso/uart: implement read_resource	2021-10-15 14:46:58 +00:00
cavium	src/soc to src/superio: Fix spelling errors	2021-10-05 18:07:08 +00:00
example	src: Introduce ARCH_ALL_STAGES_X86	2021-07-02 08:19:10 +00:00
intel	Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"	2021-10-15 13:00:32 +00:00
mediatek	soc/mediatek/mt8192: add tracker dump	2021-10-13 13:58:01 +00:00
nvidia	src/soc to src/superio: Fix spelling errors	2021-10-05 18:07:08 +00:00
qualcomm	soc/qualcomm/sc7280: Enable compression of SHRM	2021-10-15 15:38:34 +00:00
rockchip	mipi: Make panel init callback work directly on DSI transaction types	2021-09-11 01:42:47 +00:00
samsung	src/soc to src/superio: Fix spelling errors	2021-10-05 18:07:08 +00:00
sifive	src/soc to src/superio: Fix spelling errors	2021-10-05 18:07:08 +00:00
ti
ucb