Huayang Duan 63ee16075e soc/mediatek/mt8183: Enable CA perbit mechanism ... LPDDR4x has 6 CA PINs, but for some 8GB LPDDR4X DDR, the left margin of some CA PIN window is too small than others. Need to enable the CA perbit mechanism to avoid those risks. BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I58e29d0c91a469112b0b1292da80bcb802322d47 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41965 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-09-25 01:33:11 +00:00
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common	soc/mediatek/mt8192: Add mtcmos init support	2020-09-17 06:56:31 +00:00
mt8173	soc/mediatek: move power status bits under each chip	2020-09-16 07:48:20 +00:00
mt8183	soc/mediatek/mt8183: Enable CA perbit mechanism	2020-09-25 01:33:11 +00:00
mt8192	soc/mediatek/mt8192: Init PLL in bootblock	2020-09-17 06:56:55 +00:00
Kconfig