coreboot-kgpe-d16/src
Aaron Durbin 95c4344a20 arch/x86: provide common ACPI_Sx constants
Instead of open coding the literal values provide more
semantic symbol to be used. This will allow for aligning
chipset code with this as well to reduce duplication.

BUG=chrome-os-partner:54977

Change-Id: I022bf1eb258f7244f2e5aa2fb72b7b82e1900a5c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15663
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-15 08:30:13 +02:00
..
acpi
arch arch/x86: provide common ACPI_Sx constants 2016-07-15 08:30:13 +02:00
commonlib region: Add writeat and eraseat support 2016-06-24 20:48:12 +02:00
console console/post: be explicit about conditional cmos_post_log() compiling 2016-05-25 18:04:11 +02:00
cpu intel post-car: Consolidate choose_top_of_stack() 2016-07-10 11:16:07 +02:00
device device: i2c: Add support for I2C bus operations 2016-06-09 17:05:40 +02:00
drivers drivers/i2c: Add new driver for RTC type PCF8523 2016-07-14 07:04:04 +02:00
ec google/chromeec: Update EC command header 2016-07-10 03:54:07 +02:00
include tpm2: implement locking firmware rollback counter 2016-07-14 00:00:14 +02:00
lib lib/version: Correct whitespace alignment 2016-07-15 00:10:50 +02:00
mainboard Google Mainboards: Increase RO coreboot size on flash 2016-07-15 00:37:52 +02:00
northbridge nb/intel/pineview/northbridge.c: Remove legacy_hole_size_k declaration 2016-07-14 00:02:24 +02:00
soc soc/intel/skylake: don't duplicate setting ACPI sleep state 2016-07-15 08:29:59 +02:00
southbridge Documentation: Fix doxygen errors 2016-07-12 22:41:02 +02:00
superio sio/winbond/w83667hg-a: Add pinmux defines for UART B 2016-05-29 19:34:54 +02:00
vendorcode chromeos: Fill in the firmware id (RO, RW A, RW B) FMAP sections 2016-07-15 00:40:19 +02:00
Kconfig Romstage spinlocks require EARLY_CBMEM_INIT 2016-07-10 04:03:31 +02:00