9602483607
1. Add a new variable to GNVS to store information during S3 suspend whether UART debug port controller is enabled. 2. On resume, read stored GNVS variable to decide if UART debug port controller needs to be initialized. 3. Provide helpers functions required by intel/common UART driver for enabling controller on S3 resume. BUG=b:64030366 TEST=Verified behavior with different combinations: 1. Serial console enabled in coreboot: No change in behavior. 2. Serial console enabled only in kernel: coreboot initializes debug controller on S3 resume. 3. Serial console not enabled in coreboot and kernel: coreboot skips initialization of debug controller on S3 resume. Change-Id: Iad1cc974bc396ecd55b05ebb6591eec6cedfa16c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20886 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
102 lines
2.6 KiB
Makefile
102 lines
2.6 KiB
Makefile
ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y)
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subdirs-y += nhlt
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subdirs-y += romstage
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subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/intel/turbo
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subdirs-y += ../../../cpu/x86/lapic
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subdirs-y += ../../../cpu/x86/mtrr
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subdirs-y += ../../../cpu/x86/smm
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subdirs-y += ../../../cpu/x86/tsc
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bootblock-y += bootblock/bootblock.c
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bootblock-y += bootblock/cpu.c
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bootblock-y += i2c.c
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bootblock-y += bootblock/pch.c
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bootblock-y += bootblock/report_platform.c
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bootblock-$(CONFIG_UART_DEBUG) += bootblock/uart.c
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bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c
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bootblock-y += gpio.c
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bootblock-y += gspi.c
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bootblock-y += pch.c
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bootblock-y += pmutil.c
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bootblock-y += spi.c
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verstage-y += gspi.c
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verstage-y += pch.c
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verstage-$(CONFIG_UART_DEBUG) += uart_debug.c
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verstage-y += pmutil.c
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verstage-y += i2c.c
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verstage-y += spi.c
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romstage-y += gpio.c
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romstage-y += gspi.c
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romstage-y += i2c.c
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romstage-y += memmap.c
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romstage-y += me.c
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romstage-y += pch.c
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romstage-y += pei_data.c
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romstage-y += pmutil.c
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romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
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romstage-y += spi.c
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romstage-$(CONFIG_UART_DEBUG) += uart_debug.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
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ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += chip.c
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ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += chip_fsp20.c
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ramstage-y += cpu.c
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ramstage-y += dsp.c
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ramstage-y += elog.c
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ramstage-y += finalize.c
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ramstage-y += gpio.c
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ramstage-y += gspi.c
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ramstage-y += i2c.c
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ramstage-y += igd.c
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ramstage-y += irq.c
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ramstage-y += lpc.c
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ramstage-y += me.c
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ramstage-y += memmap.c
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ramstage-y += pch.c
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ramstage-y += pei_data.c
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ramstage-y += pmc.c
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ramstage-y += pmutil.c
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ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
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ramstage-y += sd.c
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ramstage-y += smi.c
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ramstage-y += smmrelocate.c
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ramstage-y += spi.c
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ramstage-y += systemagent.c
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ramstage-y += uart.c
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ramstage-$(CONFIG_UART_DEBUG) += uart_debug.c
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ramstage-y += vr_config.c
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smm-y += gpio.c
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smm-y += pch.c
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smm-y += pmutil.c
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smm-y += smihandler.c
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smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
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smm-$(CONFIG_UART_DEBUG) += uart_debug.c
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smm-y += uart.c
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postcar-y += memmap.c
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postcar-$(CONFIG_UART_DEBUG) += uart_debug.c
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# cpu_microcode_bins += ???
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CPPFLAGS_common += -I$(src)/soc/intel/skylake
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CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
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ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y)
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CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp11
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CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake
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else
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CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp20
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CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/skykabylake
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endif
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# Currently used for microcode path.
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CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR)
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ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi -O2
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endif
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