fc9fcf7414
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6008 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
115 lines
3.3 KiB
C
115 lines
3.3 KiB
C
#include <cpu/amd/gx2def.h>
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static void sdram_set_registers(const struct mem_controller *ctrl)
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{
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}
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/* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
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* Section 4.1.4, GX/CS5535 GeodeROM Porting guide */
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static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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{
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int i;
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msr_t msr;
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/* 2. clock gating for PMode */
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msr = rdmsr(MC_GLD_MSR_PM);
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msr.lo &= ~0x04;
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msr.lo |= 0x01;
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wrmsr(MC_GLD_MSR_PM, msr);
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/* undocmented bits in GX, in LX there are
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* 8 bits in PM1_UP_DLY */
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msr = rdmsr(MC_CF1017_DATA);
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msr.lo = 0x0101;
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wrmsr(MC_CF1017_DATA, msr);
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//print_debug("sdram_enable step 2\n");
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/* 3. release CKE mask to enable CKE */
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msr = rdmsr(MC_CFCLK_DBUG);
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msr.lo &= ~(0x03 << 8);
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wrmsr(MC_CFCLK_DBUG, msr);
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//print_debug("sdram_enable step 3\n");
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/* 4. set and clear REF_TST 16 times, more shouldn't hurt
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* why this is before EMRS and MRS ? */
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for (i = 0; i < 19; i++) {
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msr = rdmsr(MC_CF07_DATA);
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msr.lo |= (0x01 << 3);
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wrmsr(MC_CF07_DATA, msr);
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msr.lo &= ~(0x01 << 3);
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wrmsr(MC_CF07_DATA, msr);
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}
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//print_debug("sdram_enable step 4\n");
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/* 5. set refresh interval */
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msr = rdmsr(0x20000018);
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msr.lo &= ~(0xffff << 8);
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msr.lo |= (0x34 << 8);
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wrmsr(0x20000018, msr);
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/* set refresh staggering to 4 SDRAM clocks */
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msr = rdmsr(0x20000018);
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msr.lo &= ~(0x03 << 6);
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msr.lo |= (0x00 << 6);
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wrmsr(0x20000018, msr);
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//print_debug("sdram_enable step 5\n");
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/* 6. enable DLL, load Extended Mode Register by set and clear PROG_DRAM */
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msr = rdmsr(MC_CF07_DATA);
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msr.lo |= ((0x01 << 28) | 0x01);
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wrmsr(MC_CF07_DATA, msr);
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msr.lo &= ~((0x01 << 28) | 0x01);
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wrmsr(MC_CF07_DATA, msr);
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//print_debug("sdram_enable step 6\n");
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/* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,
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* it is documented in LX datasheet */
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/* load Mode Register by set and clear PROG_DRAM */
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msr = rdmsr(MC_CF07_DATA);
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msr.lo |= ((0x01 << 27) | 0x01);
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wrmsr(MC_CF07_DATA, msr);
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msr.lo &= ~((0x01 << 27) | 0x01);
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wrmsr(MC_CF07_DATA, msr);
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//print_debug("sdram_enable step 7\n");
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/* 8. load Mode Register by set and clear PROG_DRAM */
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msr = rdmsr(MC_CF07_DATA);
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msr.lo |= 0x01;
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wrmsr(MC_CF07_DATA, msr);
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msr.lo &= ~0x01;
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wrmsr(MC_CF07_DATA, msr);
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//print_debug("sdram_enable step 8\n");
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/* wait 200 SDCLKs */
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for (i = 0; i < 200; i++)
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outb(0xaa, 0x80);
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/* load RDSYNC */
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msr = rdmsr(MC_CF_RDSYNC);
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msr.hi = 0x000ff310;
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/* the above setting is supposed to be good for "slow" ram. We have found that for
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* some dram, at some clock rates, e.g. hynix at 366/244, this will actually
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* cause errors. The fix is to just set it to 0x310. Tested on 3 boards
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* with 3 different type of dram -- Hynix, PSC, infineon.
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* I am leaving this comment here so that at some future time nobody is tempted
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* to mess with this setting -- RGM, 9/2006
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*/
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msr.hi = 0x00000310;
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msr.lo = 0x00000000;
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wrmsr(MC_CF_RDSYNC, msr);
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/* set delay control */
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msr = rdmsr(GLCP_DELAY_CONTROLS);
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msr.hi = 0x830d415a;
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msr.lo = 0x8ea0ad6a;
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wrmsr(GLCP_DELAY_CONTROLS, msr);
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/* The RAM dll needs a write to lock on so generate a few dummy writes */
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/* Note: The descriptor needs to be enabled to point at memory */
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volatile unsigned long *ptr;
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for (i = 0; i < 5; i++) {
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ptr = (void *)i;
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*ptr = (unsigned long)i;
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}
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print_info("RAM DLL lock\n");
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}
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