149c4c5d01
We currently race in SMM init on Atom 230 (and potentially other CPUs). At least on the 230, this leads to a hang on RSM, likely because both hyperthreads mess around with SMBASE and other SMM state variables in parallel without coordination. The same behaviour occurs with Atom D5xx. Change it so first APs are spun up and sent to sleep, then BSP initializes SMM, then every CPU, one after another. Only do this when SERIALIZE_SMM_INITIALIZATION is set. Set the flag for Atom CPUs. Change-Id: I1ae864e37546298ea222e81349c27cf774ed251f Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/6311 Tested-by: build bot (Jenkins) Tested-by: BSI firmware lab <coreboot-labor@bsi.bund.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
151 lines
3.3 KiB
Text
151 lines
3.3 KiB
Text
config PARALLEL_CPU_INIT
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bool
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default n
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config UDELAY_IO
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bool
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default y if !UDELAY_LAPIC && !UDELAY_TSC && !UDELAY_TIMER2
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default n
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config UDELAY_LAPIC
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bool
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default n
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config LAPIC_MONOTONIC_TIMER
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def_bool n
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depends on UDELAY_LAPIC
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select HAVE_MONOTONIC_TIMER
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help
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Expose monotonic time using the local apic.
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config UDELAY_LAPIC_FIXED_FSB
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int
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config UDELAY_TSC
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bool
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default n
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config TSC_CONSTANT_RATE
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def_bool n
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depends on UDELAY_TSC
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help
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This option asserts that the TSC ticks at a known constant rate.
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Therefore, no TSC calibration is required.
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config TSC_MONOTONIC_TIMER
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def_bool n
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depends on UDELAY_TSC
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select HAVE_MONOTONIC_TIMER
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help
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Expose monotonic time using the TSC.
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config UDELAY_TIMER2
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bool
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default n
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config TSC_CALIBRATE_WITH_IO
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bool
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default n
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config TSC_SYNC_LFENCE
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bool
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default n
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help
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The CPU driver should select this if the CPU needs
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to execute an lfence instruction in order to synchronize
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rdtsc. This is true for all modern AMD CPUs.
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config TSC_SYNC_MFENCE
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bool
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default n
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help
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The CPU driver should select this if the CPU needs
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to execute an mfence instruction in order to synchronize
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rdtsc. This is true for all modern Intel CPUs.
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config XIP_ROM_SIZE
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hex
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default ROM_SIZE if ROMCC
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default 0x10000
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config CPU_ADDR_BITS
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int
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default 36
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config LOGICAL_CPUS
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bool
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default y
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config SMM_TSEG
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bool
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default n
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select RELOCATABLE_MODULES
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config SMM_MODULE_HEAP_SIZE
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hex
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default 0x4000
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depends on SMM_TSEG
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help
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This option determines the size of the heap within the SMM handler
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modules.
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config SMM_LAPIC_REMAP_MITIGATION
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bool
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default y if NORTHBRIDGE_INTEL_I945
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default y if NORTHBRIDGE_INTEL_GM45
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default y if NORTHBRIDGE_INTEL_NEHALEM
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default n
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config SERIALIZED_SMM_INITIALIZATION
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bool
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default n
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help
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On some CPUs, there is a race condition in SMM.
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This can occur when both hyperthreads change SMM state
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variables in parallel without coordination.
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Setting this option serializes the SMM initialization
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to avoid an ugly hang in the boot process at the cost
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of a slightly longer boot time.
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config X86_AMD_FIXED_MTRRS
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bool
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default n
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help
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This option informs the MTRR code to use the RdMem and WrMem fields
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in the fixed MTRR MSRs.
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config PLATFORM_USES_FSP1_0
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bool
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default n
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help
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Selected for Intel processors/platform combinations that use the
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Intel Firmware Support Package (FSP) 1.0 for initialization.
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config PARALLEL_MP
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def_bool n
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help
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This option uses common MP infrastructure for bringing up APs
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in parallel. It additionally provides a more flexible mechanism
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for sequencing the steps of bringing up the APs.
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config BACKUP_DEFAULT_SMM_REGION
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def_bool n
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help
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The CPU support will select this option if the default SMM region
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needs to be backed up for suspend/resume purposes.
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config MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING
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def_bool n
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help
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On certain platforms a boot speed gain can be realized if mirroring
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the payload data stored in non-volatile storage. On x86 systems the
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payload would typically live in a memory-mapped SPI part. Copying
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the SPI contents to RAM before performing the load can speed up
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the boot process.
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config BOOT_MEDIA_SPI_BUS
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int
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default 0
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depends on SPI_FLASH
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help
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Most x86 systems which boot from SPI flash boot using bus 0.
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