00809ebf02
targets/*/*/Makefile
targets/*/*/normal/Makefile
targets/*/*/fallback/Makefile
to use a common copy of romcc, and to leave this compiler untouched by
'make clean' in targets/*/*/fallback/ and targets/*/*/normal/ .
'make clean' in targets/*/*/ will clean romcc.
Thanks to Mats for the initial idea and implementation of a tool to do
this. This patch has almost the same behaviour as the original tool
without having to run the tool each time.
Tested for abuild-friendliness.
The patch saves ~10-12 seconds for every target using romcc. For a full
abuild run, this is ~20% time saved.
For the first 38 abuild targets, total build time is down to 13m24s
instead of 16m22s on my machine.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
135 lines
4.6 KiB
Text
135 lines
4.6 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
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else
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default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
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default ROM_SECTION_OFFSET = 0
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end
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default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
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+ ROM_SECTION_OFFSET + 1)
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default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
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default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
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default XIP_ROM_SIZE = 64 * 1024
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default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
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arch i386 end
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driver mainboard.o
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if HAVE_PIRQ_TABLE
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object irq_tables.o
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end
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makerule ./failover.E
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depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
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action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
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end
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makerule ./failover.inc
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depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
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action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
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end
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makerule ./auto.E
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# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
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depends "$(MAINBOARD)/auto.c ../romcc"
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action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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makerule ./auto.inc
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# depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
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depends "$(MAINBOARD)/auto.c ../romcc"
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action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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mainboardinit arch/i386/lib/cpu_reset.inc
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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mainboardinit cpu/x86/fpu/enable_fpu.inc
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mainboardinit cpu/x86/mmx/enable_mmx.inc
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mainboardinit ./auto.inc
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mainboardinit cpu/x86/mmx/disable_mmx.inc
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dir /pc80
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config chip.h
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chip northbridge/intel/i440bx # Northbridge
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device apic_cluster 0 on # APIC cluster
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chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
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device apic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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device pci 0.0 on end # Host bridge
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device pci 1.0 on end # PCI/AGP bridge
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chip southbridge/intel/i82371eb # Southbridge
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device pci 7.0 on # ISA bridge
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chip superio/smsc/smscsuperio # Super I/O
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device pnp 3f0.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 3f0.3 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 3f0.4 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 3f0.5 on # COM2 / IR
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 3f0.7 on # PS/2 keyboard / mouse
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1 # PS/2 keyboard interrupt
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irq 0x72 = 12 # PS/2 mouse interrupt
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end
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device pnp 3f0.8 on # Aux I/O
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end
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end
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end
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device pci 7.1 on end # IDE
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device pci 7.2 on end # USB
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device pci 7.3 on end # ACPI
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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register "ide_legacy_enable" = "1"
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# Enable UDMA/33 for higher speed if your IDE device(s) support it.
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register "ide0_drive0_udma33_enable" = "0"
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register "ide0_drive1_udma33_enable" = "0"
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register "ide1_drive0_udma33_enable" = "0"
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register "ide1_drive1_udma33_enable" = "0"
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end
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end
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end
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