389 lines
13 KiB
C
389 lines
13 KiB
C
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#include <stdio.h>
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#include <stdlib.h>
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#include "inteltool.h"
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static const io_register_t ich6_bios_cntl_registers[] = {
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{ 0x0, 1, "BIOSWE - write enable" },
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{ 0x1, 1, "BLE - lock enable" },
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{ 0x2, 6, "reserved" },
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};
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static const io_register_t ich7_bios_cntl_registers[] = {
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{ 0x0, 1, "BIOSWE - write enable" },
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{ 0x1, 1, "BLE - lock enable" },
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{ 0x2, 2, "SPI Read configuration" },
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{ 0x4, 1, "TopSwapStatus" },
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{ 0x5, 3, "reserved" },
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};
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static const io_register_t pch_bios_cntl_registers[] = {
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{ 0x0, 1, "BIOSWE - write enable" },
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{ 0x1, 1, "BLE - lock enable" },
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{ 0x2, 2, "SPI Read configuration" },
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{ 0x4, 1, "TopSwapStatus" },
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{ 0x5, 1, "SMM BIOS Write Protect Disable" },
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{ 0x6, 2, "reserved" },
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};
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#define ICH9_SPIBAR 0x3800
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#define ICH78_SPIBAR 0x3020
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static const io_register_t spi_bar_registers[] = {
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{ 0x00, 4, "BFPR - BIOS Flash primary region" },
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{ 0x04, 2, "HSFSTS - Hardware Sequencing Flash Status" },
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{ 0x06, 2, "HSFCTL - Hardware Sequencing Flash Control" },
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{ 0x08, 4, "FADDR - Flash Address" },
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{ 0x0c, 4, "Reserved" },
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{ 0x10, 4, "FDATA0" },
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/* 0x10 .. 0x4f are filled with data */
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{ 0x50, 4, "FRACC - Flash Region Access Permissions" },
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{ 0x54, 4, "Flash Region 0" },
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{ 0x58, 4, "Flash Region 1" },
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{ 0x5c, 4, "Flash Region 2" },
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{ 0x60, 4, "Flash Region 3" },
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{ 0x64, 4, "Flash Region 4" },
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{ 0x74, 4, "FPR0 Flash Protected Range 0" },
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{ 0x78, 4, "FPR0 Flash Protected Range 1" },
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{ 0x7c, 4, "FPR0 Flash Protected Range 2" },
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{ 0x80, 4, "FPR0 Flash Protected Range 3" },
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{ 0x84, 4, "FPR0 Flash Protected Range 4" },
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{ 0x90, 1, "SSFSTS - Software Sequencing Flash Status" },
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{ 0x91, 3, "SSFSTS - Software Sequencing Flash Status" },
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{ 0x94, 2, "PREOP - Prefix opcode Configuration" },
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{ 0x96, 2, "OPTYPE - Opcode Type Configuration" },
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{ 0x98, 8, "OPMENU - Opcode Menu Configuration" },
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{ 0xa0, 1, "BBAR - BIOS Base Address Configuration" },
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{ 0xb0, 4, "FDOC - Flash Descriptor Observability Control" },
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{ 0xb8, 4, "Reserved" },
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{ 0xc0, 4, "AFC - Additional Flash Control" },
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{ 0xc4, 4, "LVSCC - Host Lower Vendor Specific Component Capabilities" },
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{ 0xc8, 4, "UVSCC - Host Upper Vendor Specific Component Capabilities" },
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{ 0xd0, 4, "FPB - Flash Partition Boundary" },
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};
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static const io_register_t ich7_spi_bar_registers[] = {
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{ 0x00, 2, "SPIS - SPI Status" },
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{ 0x02, 2, "SPIC - SPI Control" },
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{ 0x04, 4, "SPIA - SPI Address" },
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/*
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*0x08 .. 0x47 are filled with data
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*0x48 .. 0x4f is not mentioned by datasheet
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*/
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{ 0x50, 4, "BBAR - BIOS Base Address Configuration" },
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{ 0x54, 2, "PREOP Prefix Opcode Configuration" },
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{ 0x56, 2, "OPTYPE Opcode Type Configuration" },
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{ 0x58, 8, "OPMENU Opcode Menu Configuration" },
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{ 0x60, 4, "PBR0 Protected BIOS Range 0" },
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{ 0x64, 4, "PBR1 Protected BIOS Range 1" },
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{ 0x68, 4, "PBR2 Protected BIOS Range 2" },
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};
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static int print_bioscntl(struct pci_dev *sb)
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{
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int i, size = 0;
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unsigned char bios_cntl = 0xff;
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const io_register_t *bios_cntl_register = NULL;
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printf("\n============= SPI / BIOS CNTL =============\n\n");
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switch (sb->device_id) {
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case PCI_DEVICE_ID_INTEL_ICH6:
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bios_cntl = pci_read_byte(sb, 0xdc);
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bios_cntl_register = ich6_bios_cntl_registers;
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size = ARRAY_SIZE(ich6_bios_cntl_registers);
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break;
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case PCI_DEVICE_ID_INTEL_ICH7:
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case PCI_DEVICE_ID_INTEL_ICH7M:
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case PCI_DEVICE_ID_INTEL_ICH7DH:
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case PCI_DEVICE_ID_INTEL_ICH7MDH:
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case PCI_DEVICE_ID_INTEL_ICH8:
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case PCI_DEVICE_ID_INTEL_ICH8M:
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case PCI_DEVICE_ID_INTEL_ICH8ME:
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case PCI_DEVICE_ID_INTEL_ICH9DH:
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case PCI_DEVICE_ID_INTEL_ICH9DO:
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case PCI_DEVICE_ID_INTEL_ICH9R:
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case PCI_DEVICE_ID_INTEL_ICH9:
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case PCI_DEVICE_ID_INTEL_ICH9M:
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case PCI_DEVICE_ID_INTEL_ICH9ME:
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case PCI_DEVICE_ID_INTEL_ICH10:
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case PCI_DEVICE_ID_INTEL_ICH10R:
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case PCI_DEVICE_ID_INTEL_NM10:
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bios_cntl = pci_read_byte(sb, 0xdc);
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bios_cntl_register = ich7_bios_cntl_registers;
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size = ARRAY_SIZE(ich7_bios_cntl_registers);
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break;
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case PCI_DEVICE_ID_INTEL_3400:
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case PCI_DEVICE_ID_INTEL_3420:
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case PCI_DEVICE_ID_INTEL_3450:
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case PCI_DEVICE_ID_INTEL_3400_DESKTOP:
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case PCI_DEVICE_ID_INTEL_B55_A:
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case PCI_DEVICE_ID_INTEL_B55_B:
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case PCI_DEVICE_ID_INTEL_H55:
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case PCI_DEVICE_ID_INTEL_H57:
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case PCI_DEVICE_ID_INTEL_P55:
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case PCI_DEVICE_ID_INTEL_Q57:
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case PCI_DEVICE_ID_INTEL_3400_MOBILE:
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case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF:
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case PCI_DEVICE_ID_INTEL_HM55:
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case PCI_DEVICE_ID_INTEL_HM57:
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case PCI_DEVICE_ID_INTEL_PM55:
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case PCI_DEVICE_ID_INTEL_QM57:
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case PCI_DEVICE_ID_INTEL_QS57:
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case PCI_DEVICE_ID_INTEL_Z68:
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case PCI_DEVICE_ID_INTEL_P67:
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case PCI_DEVICE_ID_INTEL_UM67:
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case PCI_DEVICE_ID_INTEL_HM65:
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case PCI_DEVICE_ID_INTEL_H67:
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case PCI_DEVICE_ID_INTEL_HM67:
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case PCI_DEVICE_ID_INTEL_Q65:
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case PCI_DEVICE_ID_INTEL_QS67:
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case PCI_DEVICE_ID_INTEL_Q67:
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case PCI_DEVICE_ID_INTEL_QM67:
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case PCI_DEVICE_ID_INTEL_B65:
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case PCI_DEVICE_ID_INTEL_C202:
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case PCI_DEVICE_ID_INTEL_C204:
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case PCI_DEVICE_ID_INTEL_C206:
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case PCI_DEVICE_ID_INTEL_H61:
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case PCI_DEVICE_ID_INTEL_Z77:
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case PCI_DEVICE_ID_INTEL_Z75:
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case PCI_DEVICE_ID_INTEL_Q77:
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case PCI_DEVICE_ID_INTEL_Q75:
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case PCI_DEVICE_ID_INTEL_B75:
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case PCI_DEVICE_ID_INTEL_H77:
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case PCI_DEVICE_ID_INTEL_C216:
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case PCI_DEVICE_ID_INTEL_QM77:
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case PCI_DEVICE_ID_INTEL_QS77:
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case PCI_DEVICE_ID_INTEL_HM77:
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case PCI_DEVICE_ID_INTEL_UM77:
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case PCI_DEVICE_ID_INTEL_HM76:
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case PCI_DEVICE_ID_INTEL_HM75:
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case PCI_DEVICE_ID_INTEL_HM70:
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case PCI_DEVICE_ID_INTEL_NM70:
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case PCI_DEVICE_ID_INTEL_C8_MOBILE:
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case PCI_DEVICE_ID_INTEL_C8_DESKTOP:
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case PCI_DEVICE_ID_INTEL_Z87:
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case PCI_DEVICE_ID_INTEL_Z85:
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case PCI_DEVICE_ID_INTEL_HM86:
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case PCI_DEVICE_ID_INTEL_H87:
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case PCI_DEVICE_ID_INTEL_HM87:
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case PCI_DEVICE_ID_INTEL_Q85:
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case PCI_DEVICE_ID_INTEL_Q87:
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case PCI_DEVICE_ID_INTEL_QM87:
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case PCI_DEVICE_ID_INTEL_B85:
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case PCI_DEVICE_ID_INTEL_C222:
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case PCI_DEVICE_ID_INTEL_C224:
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case PCI_DEVICE_ID_INTEL_C226:
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case PCI_DEVICE_ID_INTEL_H81:
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case PCI_DEVICE_ID_INTEL_H110:
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case PCI_DEVICE_ID_INTEL_H170:
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case PCI_DEVICE_ID_INTEL_Z170:
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case PCI_DEVICE_ID_INTEL_Q170:
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case PCI_DEVICE_ID_INTEL_Q150:
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case PCI_DEVICE_ID_INTEL_B150:
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case PCI_DEVICE_ID_INTEL_C236:
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case PCI_DEVICE_ID_INTEL_C232:
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case PCI_DEVICE_ID_INTEL_QM170:
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case PCI_DEVICE_ID_INTEL_HM170:
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case PCI_DEVICE_ID_INTEL_CM236:
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case PCI_DEVICE_ID_INTEL_HM175:
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case PCI_DEVICE_ID_INTEL_QM175:
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case PCI_DEVICE_ID_INTEL_CM238:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
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bios_cntl = pci_read_byte(sb, 0xdc);
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bios_cntl_register = pch_bios_cntl_registers;
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size = ARRAY_SIZE(pch_bios_cntl_registers);
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break;
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default:
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printf("Error: Dumping SPI on this southbridge is not (yet) supported.\n");
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return 1;
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}
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printf("BIOS_CNTL = 0x%04x (IO)\n\n", bios_cntl);
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if (bios_cntl_register) {
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for (i = 0; i < size; i++) {
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unsigned int val = bios_cntl >> bios_cntl_register[i].addr;
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val &= ((1 << bios_cntl_register[i].size) -1);
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printf("0x%04x = %s\n", val, bios_cntl_register[i].name);
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}
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}
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return 0;
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}
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static int print_spibar(struct pci_dev *sb) {
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int i, size = 0, rcba_size = 0x4000;
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volatile uint8_t *rcba;
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uint32_t rcba_phys;
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const io_register_t *spi_register = NULL;
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uint32_t spibaroffset;
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printf("\n============= SPI Bar ==============\n\n");
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switch (sb->device_id) {
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case PCI_DEVICE_ID_INTEL_ICH6:
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printf("This southbridge does not have a SPI controller.\n");
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return 1;
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case PCI_DEVICE_ID_INTEL_ICH7:
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case PCI_DEVICE_ID_INTEL_ICH7M:
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case PCI_DEVICE_ID_INTEL_ICH7DH:
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case PCI_DEVICE_ID_INTEL_ICH7MDH:
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spibaroffset = ICH78_SPIBAR;
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rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
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size = ARRAY_SIZE(ich7_spi_bar_registers);
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spi_register = ich7_spi_bar_registers;
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break;
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case PCI_DEVICE_ID_INTEL_ICH8:
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spibaroffset = ICH78_SPIBAR;
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rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
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size = ARRAY_SIZE(spi_bar_registers);
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spi_register = spi_bar_registers;
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break;
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case PCI_DEVICE_ID_INTEL_ICH8M:
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case PCI_DEVICE_ID_INTEL_ICH8ME:
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case PCI_DEVICE_ID_INTEL_ICH9DH:
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case PCI_DEVICE_ID_INTEL_ICH9DO:
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case PCI_DEVICE_ID_INTEL_ICH9R:
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case PCI_DEVICE_ID_INTEL_ICH9:
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case PCI_DEVICE_ID_INTEL_ICH9M:
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case PCI_DEVICE_ID_INTEL_ICH9ME:
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case PCI_DEVICE_ID_INTEL_ICH10:
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case PCI_DEVICE_ID_INTEL_ICH10R:
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case PCI_DEVICE_ID_INTEL_NM10:
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case PCI_DEVICE_ID_INTEL_I63XX:
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case PCI_DEVICE_ID_INTEL_3400:
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case PCI_DEVICE_ID_INTEL_3420:
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case PCI_DEVICE_ID_INTEL_3450:
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case PCI_DEVICE_ID_INTEL_3400_DESKTOP:
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case PCI_DEVICE_ID_INTEL_3400_MOBILE:
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case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF:
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case PCI_DEVICE_ID_INTEL_B55_A:
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case PCI_DEVICE_ID_INTEL_B55_B:
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case PCI_DEVICE_ID_INTEL_H55:
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case PCI_DEVICE_ID_INTEL_H57:
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case PCI_DEVICE_ID_INTEL_HM55:
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case PCI_DEVICE_ID_INTEL_HM57:
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case PCI_DEVICE_ID_INTEL_P55:
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case PCI_DEVICE_ID_INTEL_PM55:
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case PCI_DEVICE_ID_INTEL_Q57:
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case PCI_DEVICE_ID_INTEL_QM57:
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case PCI_DEVICE_ID_INTEL_QS57:
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case PCI_DEVICE_ID_INTEL_Z68:
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case PCI_DEVICE_ID_INTEL_P67:
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case PCI_DEVICE_ID_INTEL_UM67:
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case PCI_DEVICE_ID_INTEL_HM65:
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case PCI_DEVICE_ID_INTEL_H67:
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case PCI_DEVICE_ID_INTEL_HM67:
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case PCI_DEVICE_ID_INTEL_Q65:
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case PCI_DEVICE_ID_INTEL_QS67:
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case PCI_DEVICE_ID_INTEL_Q67:
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case PCI_DEVICE_ID_INTEL_QM67:
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case PCI_DEVICE_ID_INTEL_B65:
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case PCI_DEVICE_ID_INTEL_C202:
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case PCI_DEVICE_ID_INTEL_C204:
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case PCI_DEVICE_ID_INTEL_C206:
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case PCI_DEVICE_ID_INTEL_H61:
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case PCI_DEVICE_ID_INTEL_Z77:
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case PCI_DEVICE_ID_INTEL_Z75:
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case PCI_DEVICE_ID_INTEL_Q77:
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case PCI_DEVICE_ID_INTEL_Q75:
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case PCI_DEVICE_ID_INTEL_B75:
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case PCI_DEVICE_ID_INTEL_H77:
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case PCI_DEVICE_ID_INTEL_C216:
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case PCI_DEVICE_ID_INTEL_QM77:
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case PCI_DEVICE_ID_INTEL_QS77:
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case PCI_DEVICE_ID_INTEL_HM77:
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case PCI_DEVICE_ID_INTEL_UM77:
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case PCI_DEVICE_ID_INTEL_HM76:
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case PCI_DEVICE_ID_INTEL_HM75:
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case PCI_DEVICE_ID_INTEL_HM70:
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case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
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case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
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case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
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case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM:
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case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
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case PCI_DEVICE_ID_INTEL_C8_MOBILE:
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case PCI_DEVICE_ID_INTEL_C8_DESKTOP:
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case PCI_DEVICE_ID_INTEL_Z87:
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case PCI_DEVICE_ID_INTEL_Z85:
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case PCI_DEVICE_ID_INTEL_HM86:
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case PCI_DEVICE_ID_INTEL_H87:
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case PCI_DEVICE_ID_INTEL_HM87:
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case PCI_DEVICE_ID_INTEL_Q85:
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case PCI_DEVICE_ID_INTEL_Q87:
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case PCI_DEVICE_ID_INTEL_QM87:
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case PCI_DEVICE_ID_INTEL_B85:
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case PCI_DEVICE_ID_INTEL_C222:
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case PCI_DEVICE_ID_INTEL_C224:
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case PCI_DEVICE_ID_INTEL_C226:
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case PCI_DEVICE_ID_INTEL_H81:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
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spibaroffset = ICH9_SPIBAR;
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rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
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size = ARRAY_SIZE(spi_bar_registers);
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spi_register = spi_bar_registers;
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break;
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case PCI_DEVICE_ID_INTEL_ICH:
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case PCI_DEVICE_ID_INTEL_ICH0:
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case PCI_DEVICE_ID_INTEL_ICH2:
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case PCI_DEVICE_ID_INTEL_ICH4:
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case PCI_DEVICE_ID_INTEL_ICH4M:
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case PCI_DEVICE_ID_INTEL_ICH5:
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printf("This southbridge does not have RCBA.\n");
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return 1;
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default:
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printf("Error: Dumping RCBA on this southbridge is not (yet) supported.\n");
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return 1;
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}
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rcba = map_physical(rcba_phys, rcba_size);
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if (rcba == NULL) {
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perror("Error mapping RCBA");
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exit(1);
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}
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for (i = 0; i < size; i++) {
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switch(spi_register[i].size) {
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case 1:
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printf("0x%08x = %s\n", *(uint8_t *)(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name);
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break;
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case 2:
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printf("0x%08x = %s\n", *(uint16_t *)(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name);
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break;
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case 4:
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printf("0x%08x = %s\n", *(uint32_t *)(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name);
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break;
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case 8:
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printf("0x%08x%08x = %s\n", *(uint32_t *)(rcba + spibaroffset + spi_register[i].addr + 4),
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*(uint32_t *)(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name);
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break;
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}
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}
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unmap_physical((void *)rcba, rcba_size);
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return 0;
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}
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|
|
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int print_spi(struct pci_dev *sb) {
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|
return (print_bioscntl(sb) || print_spibar(sb));
|
|
}
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