4c8d4872a5
This patch refactor cbmem and timer code which will be reused among
similar SOCs.
BUG=b:80501386
BRANCH=none
TEST=the refactored code works fine on the new platform (with the rest
of the patches applied) and Elm platform
Change-Id: I397ebdc0c97c7616bd547022d2ce2a8f08f3c232
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26881
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
35 lines
1 KiB
C
35 lines
1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <soc/mcucfg.h>
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#include <soc/timer.h>
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void timer_prepare(void)
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{
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/* Set XGPT_IDX to 0, then the bit field of XGPT_CTL will be programmed
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* with following definition.
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*
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* [10: 8] Clock mode
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* 100: 26Mhz / 4
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* 010: 26Mhz / 2
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* 001: 26Mhz
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* [ 1: 1] Halt-on-debug enable bit
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* [ 0: 0] XGPT enable bit
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*/
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write32(&mt8173_mcucfg->xgpt_idx, 0);
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/* Set clock mode to 13Mhz and enable XGPT */
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write32(&mt8173_mcucfg->xgpt_ctl, (0x1 | ((26 / GPT4_MHZ) << 8)));
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}
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