cff071ab0e
files for targets without failover: src/config/nofailovercalculation.lb (64 kB XIP) src/config/nofailovercalculation128.lb (128 kB XIP) Targets with other XIP sizes were ignored. This patch moves XIP size back into mainboard code. Benefits from this patch: - src/config/nofailovercalculation128.lb is no longer needed - Targets with XIP sizes besides 64k and 128k benefit from refactoring - Conceptually, this makes the include files pure calculation files without settings. Abuild tested. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4348 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
139 lines
4.7 KiB
Text
139 lines
4.7 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2008 VIA Technologies, Inc.
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## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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## XIP_ROM_SIZE must be a power of 2.
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default XIP_ROM_SIZE = 64 * 1024
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include /config/nofailovercalculation.lb
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arch i386 end
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driver mainboard.o
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if HAVE_PIRQ_TABLE object irq_tables.o end
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_ACPI_TABLES
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object fadt.o
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object dsdt.o
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object acpi_tables.o
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end
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makerule ./failover.E
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depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
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action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
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end
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makerule ./failover.inc
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depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
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action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
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end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
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action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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makerule ./auto.inc
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depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
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action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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mainboardinit arch/i386/lib/cpu_reset.inc
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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mainboardinit cpu/x86/fpu/enable_fpu.inc
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mainboardinit cpu/x86/mmx/enable_mmx.inc
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mainboardinit ./auto.inc
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mainboardinit cpu/x86/mmx/disable_mmx.inc
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dir /pc80
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config chip.h
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chip northbridge/via/cn700 # Northbridge
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device pci_domain 0 on # PCI domain
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device pci 0.0 on end # AGP Bridge
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device pci 0.1 on end # Error Reporting
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device pci 0.2 on end # Host Bus Control
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device pci 0.3 on end # Memory Controller
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device pci 0.4 on end # Power Management
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device pci 0.7 on end # V-Link Controller
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device pci 1.0 on end # PCI Bridge
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chip southbridge/via/vt8237r # Southbridge
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# Enable both IDE channels.
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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# Both cables are 40pin.
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register "ide0_80pin_cable" = "0"
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register "ide1_80pin_cable" = "0"
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register "fn_ctrl_lo" = "0x80"
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register "fn_ctrl_hi" = "0x1d"
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device pci f.0 on end # IDE
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device pci 10.0 on end # UHCI
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device pci 10.1 on end # UHCI
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device pci 10.2 on end # UHCI
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device pci 10.3 on end # UHCI
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device pci 10.4 on end # EHCI
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device pci 11.0 on # Southbridge LPC
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chip superio/winbond/w83697hf # Super I/O
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 on # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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drq 0x74 = 3
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end
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device pnp 2e.2 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on # COM2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.6 off end # Consumer IR
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device pnp 2e.7 off end # Game port, GPIO 1
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device pnp 2e.8 off end # MIDI port, GPIO 5
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device pnp 2e.9 off end # GPIO 2-4
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device pnp 2e.a off end # ACPI
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device pnp 2e.b on # HWM
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io 0x60 = 0x290
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end
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end
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end
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device pci 11.5 on end # AC'97 audio
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device pci 12.0 on end # Ethernet
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end
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end
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device apic_cluster 0 on # APIC cluster
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chip cpu/via/model_c7 # VIA C7
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device apic 0 on end # APIC
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end
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end
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end
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