6b5bc77c9b
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
101 lines
2.9 KiB
C
101 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _SOC_CHIP_H_
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#define _SOC_CHIP_H_
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#include <stdint.h>
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#include <fsp/util.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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///
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/// MRC Flags bits
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///
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#define MRC_FLAG_ECC_EN BIT0
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#define MRC_FLAG_SCRAMBLE_EN BIT1
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#define MRC_FLAG_MEMTEST_EN BIT2
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/* 0b DDR "fly-by" topology else 1b DDR "tree" topology */
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#define MRC_FLAG_TOP_TREE_EN BIT3
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/* If set ODR signal is asserted to DRAM devices on writes */
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#define MRC_FLAG_WR_ODT_EN BIT4
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struct soc_intel_quark_config {
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/*
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* MemoryInit:
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*
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* The following fields come from FspUpdVpd.h and are defined as PCDs
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* for the FSP binary. Data for these fields comes from the board's
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* devicetree.cb file which gets processed into static.c and then
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* built into the coreboot image. The fields below contain retain
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* the FSP PCD field name.
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*/
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uint32_t FspReservedMemoryLength; /* FSP reserved memory in bytes */
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uint32_t Flags; /* Bitmap of MRC_FLAG_XXX defs above */
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uint32_t tRAS; /* ACT to PRE command period in picoseconds */
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/* Delay from start of internal write transaction to internal read
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* command in picoseconds
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*/
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uint32_t tWTR;
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/* ACT to ACT command period (JESD79 specific to page size 1K/2K) in
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* picoseconds
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*/
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uint32_t tRRD;
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/* Four activate window (JESD79 specific to page size 1K/2K) in
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* picoseconds
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*/
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uint32_t tFAW;
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uint8_t DramWidth; /* 0=x8, 1=x16, others=RESERVED */
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/* 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU
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* support 1066 memory
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*/
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uint8_t DramSpeed;
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uint8_t DramType; /* 0=DDR3,1=DDR3L, others=RESERVED */
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/* bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED */
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uint8_t RankMask;
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uint8_t ChanMask; /* bit[0] CHAN0_EN, others=RESERVED */
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uint8_t ChanWidth; /* 1=x16, others=RESERVED */
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/* 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED */
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uint8_t AddrMode;
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/* 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE */
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uint8_t SrInt;
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uint8_t SrTemp; /* 0=normal, 1=extended, others=RESERVED */
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/* 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver
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* impedance control.
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*/
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uint8_t DramRonVal;
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uint8_t DramRttNomVal; /* 0=40ohm, 1=60ohm, 2=120ohm, others=RSVD */
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uint8_t DramRttWrVal; /* 0=off others=RESERVED */
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/* 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED */
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uint8_t SocRdOdtVal;
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uint8_t SocWrRonVal; /* 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED */
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uint8_t SocWrSlewRate; /* 0=2.5V/ns, 1=4V/ns, others=RESERVED */
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/* 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED */
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uint8_t DramDensity;
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uint8_t tCL; /* DRAM CAS Latency in clocks */
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/* ECC scrub interval in miliseconds 1..255 (0 works as feature
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* disable)
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*/
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uint8_t EccScrubInterval;
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/* Number of 32B blocks read for ECC scrub 2..16 */
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uint8_t EccScrubBlkSize;
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uint8_t SmmTsegSize; /* SMM size in MiB */
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};
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#endif
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