b9c1a4e8d9
The southbridge bootblock entry point bootblock_southbridge_init() just calls i82371eb_enable_rom() which does all the work. Move all that code into bootblock_southbridge_init() and drop the second function. Plus combine the 3 lines that set 3 bits in XBCS into one. Change-Id: I07a5a28c91da9586e3bdaaf4521cba3f53a5cc01 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
42 lines
1.4 KiB
C
42 lines
1.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <arch/io.h>
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#include <device/pci_ids.h>
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#include "i82371eb.h"
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static void bootblock_southbridge_init(void)
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{
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u16 reg16;
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pci_devfn_t dev;
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/*
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* Note: The Intel 82371AB/EB/MB ISA device can be on different
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* PCI bus:device.function locations on different boards.
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* Examples we encountered: 00:07.0, 00:04.0, or 00:14.0.
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* But scanning for the PCI IDs (instead of hardcoding
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* bus/device/function numbers) works on all boards.
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*/
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dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_82371AB_ISA), 0);
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/* Enable access to the whole ROM, disable ROM write access. */
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reg16 = pci_read_config16(dev, XBCS);
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reg16 |= LOWER_BIOS_ENABLE | EXT_BIOS_ENABLE | EXT_BIOS_ENABLE_1MB;
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reg16 &= ~(WRITE_PROTECT_ENABLE); /* Disable ROM write access. */
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pci_write_config16(dev, XBCS, reg16);
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}
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