coreboot-kgpe-d16/src/southbridge
Stefan Reinauer 998f3a27be Cougar/Panther Point: Compile in ME7 and ME8 code at the same time
In the short term there might be devices with Sandy Bridge CPUs
on mainboards with Panther Point PCHes. While this configuration
option is perfectly valid, coreboot currently ties Sandy Bridge to
Cougar Point and Ivy Bridge to Panther Point. One occurence is in
the ME handling code.

To make coreboot most flexible, compile both ME handlers into
coreboot and decide at runtime which one to use.

Change-Id: Icffe2930873f67c99c3f73e37e7a967f4f002b88
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1280
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24 23:17:17 +02:00
..
amd cs5536: add smbus support in ramstage 2012-07-24 12:18:28 +02:00
broadcom Clean up #ifs 2012-05-08 00:34:34 +02:00
intel Cougar/Panther Point: Compile in ME7 and ME8 code at the same time 2012-07-24 23:17:17 +02:00
nvidia Don't use 64-bit constant 0x100000000 in linker scripts 2012-06-21 08:05:31 +02:00
rdc Add support for RDC R8610 Southbridge 2012-03-27 18:39:05 +02:00
ricoh add functions to set Subsystem Vendor/Device to rl5c746 2011-02-28 18:09:58 +00:00
sis Don't use 64-bit constant 0x100000000 in linker scripts 2012-06-21 08:05:31 +02:00
ti remove trailing whitespace 2011-11-01 19:07:45 +01:00
via Define global uma_memory variables 2012-07-16 18:41:46 +02:00
Kconfig Add support for RDC R8610 Southbridge 2012-03-27 18:39:05 +02:00
Makefile.inc Add support for RDC R8610 Southbridge 2012-03-27 18:39:05 +02:00