5806665059
If the Intel IGD device pci 02.0 is disabled or undefined in the device tree, then internal graphics pre-allocated memory and GFX-VT MMIO memory for virtualization won`t be allocated in the SoC address space. Thus, patch resolves the FSP-S hang problem on Skylake/ Kaby Lake processors when the IGD device is disabled. This should provide to run FSP 2.0-based coreboot on these CPUs families without integrated graphics card. The following boards were used for testing: - Asrock H110M-DVS board (desktop i5-6600) & NVIDIA GTX 1060 as external GPU. Virtualization and GFX 3D acceleration with nouveau driver still works well (tested on VirtualBox 5.1.38 with Ubuntu 18.04.1 as guest and host OS) - Intel KBL-R U RVP board (mobile i5-8350u) without GFX. Payload: tianocore edk2-stable201811-216-g51be9d0. Change-Id: Id7a0cba582d83e3fe7e8d20342ee219cdd369a53 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32467 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
97 lines
2.8 KiB
C
97 lines
2.8 KiB
C
/*
|
|
* This file is part of the coreboot project.
|
|
*
|
|
* Copyright (C) 2007-2009 coresystems GmbH
|
|
* Copyright (C) 2014 Google Inc.
|
|
* Copyright (C) 2015-2017 Intel Corporation.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; version 2 of the License.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*/
|
|
|
|
#include <cpu/x86/msr.h>
|
|
#include <delay.h>
|
|
#include <device/device.h>
|
|
#include <device/pci_ops.h>
|
|
#include <intelblocks/systemagent.h>
|
|
#include <soc/cpu.h>
|
|
#include <soc/iomap.h>
|
|
#include <soc/msr.h>
|
|
#include <soc/pci_devs.h>
|
|
#include <soc/systemagent.h>
|
|
#include "chip.h"
|
|
|
|
bool soc_is_vtd_capable(void)
|
|
{
|
|
struct device *const root_dev = SA_DEV_ROOT;
|
|
return root_dev &&
|
|
!(pci_read_config32(root_dev, CAPID0_A) & VTD_DISABLE);
|
|
}
|
|
|
|
/*
|
|
* SoC implementation
|
|
*
|
|
* Add all known fixed memory ranges for Host Controller/Memory
|
|
* controller.
|
|
*/
|
|
void soc_add_fixed_mmio_resources(struct device *dev, int *index)
|
|
{
|
|
struct device *const igd_dev = SA_DEV_IGD;
|
|
static const struct sa_mmio_descriptor soc_fixed_resources[] = {
|
|
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
|
|
"PCIEXBAR" },
|
|
{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
|
|
{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
|
|
{ EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
|
|
{ GDXCBAR, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE, "GDXCBAR" },
|
|
{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
|
|
};
|
|
const struct soc_intel_skylake_config *const config = dev->chip_info;
|
|
|
|
sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
|
|
ARRAY_SIZE(soc_fixed_resources));
|
|
|
|
if (!(config && config->ignore_vtd) && soc_is_vtd_capable()) {
|
|
if (igd_dev && igd_dev->enabled)
|
|
sa_add_fixed_mmio_resources(dev, index,
|
|
&soc_gfxvt_mmio_descriptor, 1);
|
|
|
|
sa_add_fixed_mmio_resources(dev, index,
|
|
&soc_vtvc0_mmio_descriptor, 1);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* SoC implementation
|
|
*
|
|
* Perform System Agent Initialization during Ramstage phase.
|
|
*/
|
|
void soc_systemagent_init(struct device *dev)
|
|
{
|
|
/* Enable Power Aware Interrupt Routing */
|
|
enable_power_aware_intr();
|
|
|
|
/* Enable BIOS Reset CPL */
|
|
enable_bios_reset_cpl();
|
|
|
|
/* Configure turbo power limits 1ms after reset complete bit */
|
|
mdelay(1);
|
|
set_power_limits(28);
|
|
}
|
|
|
|
int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base,
|
|
uint64_t *prmrr_mask)
|
|
{
|
|
msr_t msr;
|
|
msr = rdmsr(MSR_UNCORE_PRMRR_PHYS_BASE);
|
|
*prmrr_base = (uint64_t) msr.hi << 32 | msr.lo;
|
|
msr = rdmsr(MSR_UNCORE_PRMRR_PHYS_MASK);
|
|
*prmrr_mask = (uint64_t) msr.hi << 32 | msr.lo;
|
|
return 0;
|
|
}
|