a50b1f9dd0
Currently the throttle event handler method THRM is defined as an extern on the intel bd82x6x and lynxpoint chipsets, then defined again in the platform with thermal event handling. In newer versions of IASL, this generates an error, as the method is defined in two places. Simply removing the extern causes the call to it to fail on platforms where it isn't actually defined, so add a preprocessor define where it's implemented, and only call the method on those platforms. This also requires moving the thermal handler, which now includes the define to before the gnvs asl file. TEST=Build before and after, make sure correct code is included. Change-Id: I7af4a346496c1352ec20bda8acb338b5d277d99b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26123 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
58 lines
1.5 KiB
Text
58 lines
1.5 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, // DSDT revision: ACPI v2.0
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"COREv4", // OEM id
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"COREBOOT", // OEM table id
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0x20110725 // OEM revision
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)
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{
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#include <southbridge/intel/bd82x6x/acpi/platform.asl>
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// Some generic macros
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#include "acpi/platform.asl"
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// Thermal handler
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#include "acpi/thermal.asl"
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// global NVS and variables
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#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
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// General Purpose Events
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//#include "acpi/gpe.asl"
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#include <cpu/intel/model_206ax/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
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#include <southbridge/intel/bd82x6x/acpi/pch.asl>
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#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
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}
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}
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#include "acpi/mainboard.asl"
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#include <vendorcode/google/chromeos/acpi/chromeos.asl>
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/* Chipset specific sleep states */
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#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
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}
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