9a380abaa2
- Convert all PCI ID lists to new scheme - Unify code (variable names) - add missing PCI IDs for Panther Point PCIe root ports. Change-Id: I6357f6ebce7ddffe45a3ec642b0c594147f6134c Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1301 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
363 lines
8.5 KiB
C
363 lines
8.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <arch/io.h>
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#include <delay.h>
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#include "pch.h"
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#define HDA_ICII_REG 0x68
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#define HDA_ICII_BUSY (1 << 0)
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#define HDA_ICII_VALID (1 << 1)
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typedef struct southbridge_intel_bd82x6x_config config_t;
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static int set_bits(u32 port, u32 mask, u32 val)
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{
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u32 reg32;
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int count;
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/* Write (val & mask) to port */
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val &= mask;
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reg32 = read32(port);
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reg32 &= ~mask;
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reg32 |= val;
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write32(port, reg32);
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/* Wait for readback of register to
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* match what was just written to it
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*/
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count = 50;
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do {
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/* Wait 1ms based on BKDG wait time */
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mdelay(1);
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reg32 = read32(port);
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reg32 &= mask;
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} while ((reg32 != val) && --count);
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/* Timeout occurred */
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if (!count)
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return -1;
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return 0;
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}
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static int codec_detect(u32 base)
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{
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u8 reg8;
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/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
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if (set_bits(base + 0x08, 1, 1) == -1)
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goto no_codec;
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/* Write back the value once reset bit is set. */
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write16(base + 0x0, read16(base + 0x0));
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/* Read in Codec location (BAR + 0xe)[2..0]*/
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reg8 = read8(base + 0xe);
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reg8 &= 0x0f;
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if (!reg8)
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goto no_codec;
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return reg8;
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no_codec:
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/* Codec Not found */
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/* Put HDA back in reset (BAR + 0x8) [0] */
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set_bits(base + 0x08, 1, 0);
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printk(BIOS_DEBUG, "Azalia: No codec!\n");
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return 0;
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}
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const u32 * cim_verb_data = NULL;
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u32 cim_verb_data_size = 0;
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static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
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{
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int idx=0;
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while (idx < (cim_verb_data_size / sizeof(u32))) {
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u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32
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if (cim_verb_data[idx] != viddid) {
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idx += verb_size + 3; // skip verb + header
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continue;
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}
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*verb = &cim_verb_data[idx+3];
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return verb_size;
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}
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/* Not all codecs need to load another verb */
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return 0;
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}
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/**
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* Wait 50usec for the codec to indicate it is ready
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* no response would imply that the codec is non-operative
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*/
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static int wait_for_ready(u32 base)
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{
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/* Use a 50 usec timeout - the Linux kernel uses the
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* same duration */
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int timeout = 50;
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while(timeout--) {
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u32 reg32 = read32(base + HDA_ICII_REG);
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if (!(reg32 & HDA_ICII_BUSY))
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return 0;
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udelay(1);
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}
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return -1;
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}
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/**
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* Wait 50usec for the codec to indicate that it accepted
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* the previous command. No response would imply that the code
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* is non-operative
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*/
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static int wait_for_valid(u32 base)
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{
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u32 reg32;
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/* Send the verb to the codec */
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reg32 = read32(base + HDA_ICII_REG);
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reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID;
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write32(base + HDA_ICII_REG, reg32);
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/* Use a 50 usec timeout - the Linux kernel uses the
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* same duration */
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int timeout = 50;
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while(timeout--) {
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reg32 = read32(base + HDA_ICII_REG);
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if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
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HDA_ICII_VALID)
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return 0;
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udelay(1);
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}
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return -1;
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}
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static void codec_init(struct device *dev, u32 base, int addr)
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{
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u32 reg32;
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const u32 *verb;
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u32 verb_size;
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int i;
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printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr);
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/* 1 */
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if (wait_for_ready(base) == -1) {
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printk(BIOS_DEBUG, " codec not ready.\n");
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return;
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}
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reg32 = (addr << 28) | 0x000f0000;
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write32(base + 0x60, reg32);
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if (wait_for_valid(base) == -1) {
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printk(BIOS_DEBUG, " codec not valid.\n");
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return;
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}
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reg32 = read32(base + 0x64);
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/* 2 */
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printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
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verb_size = find_verb(dev, reg32, &verb);
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if (!verb_size) {
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printk(BIOS_DEBUG, "Azalia: No verb!\n");
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return;
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}
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printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size);
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/* 3 */
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for (i = 0; i < verb_size; i++) {
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if (wait_for_ready(base) == -1)
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return;
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write32(base + 0x60, verb[i]);
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if (wait_for_valid(base) == -1)
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return;
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}
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printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
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}
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static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
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{
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int i;
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for (i = 3; i >= 0; i--) {
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if (codec_mask & (1 << i))
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codec_init(dev, base, i);
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}
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}
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static void azalia_init(struct device *dev)
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{
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u32 base;
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struct resource *res;
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u32 codec_mask;
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u8 reg8;
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u16 reg16;
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u32 reg32;
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/* Find base address */
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (!res)
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return;
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// NOTE this will break as soon as the Azalia get's a bar above
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// 4G. Is there anything we can do about it?
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base = (u32)res->base;
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printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
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if (RCBA32(0x2030) & (1 << 31)) {
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reg32 = pci_mmio_read_config32(dev, 0x120);
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reg32 &= 0xf8ffff01;
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reg32 |= (1 << 24); // 25 for server
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reg32 |= RCBA32(0x2030) & 0xfe;
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pci_mmio_write_config32(dev, 0x120, reg32);
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reg16 = pci_mmio_read_config16(dev, 0x78);
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reg16 &= ~(1 << 11);
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pci_mmio_write_config16(dev, 0x78, reg16);
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} else
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printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n");
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reg32 = pci_mmio_read_config32(dev, 0x114);
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reg32 &= ~0xfe;
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pci_mmio_write_config32(dev, 0x114, reg32);
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// Set VCi enable bit
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if (pci_mmio_read_config32(dev, 0x120) & ((1 << 24) |
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(1 << 25) | (1 << 26))) {
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reg32 = pci_mmio_read_config32(dev, 0x120);
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reg32 |= (1 << 31);
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pci_mmio_write_config32(dev, 0x120, reg32);
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}
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// Enable HDMI codec:
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reg32 = pci_read_config32(dev, 0xc4);
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reg32 |= (1 << 1);
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pci_write_config32(dev, 0xc4, reg32);
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reg8 = pci_read_config8(dev, 0x43);
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reg8 |= (1 << 6);
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pci_write_config8(dev, 0x43, reg8);
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/* Additional programming steps */
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reg32 = pci_read_config32(dev, 0xc4);
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reg32 |= (1 << 13) | (1 << 10);
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pci_write_config32(dev, 0xc4, reg32);
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reg32 = pci_read_config32(dev, 0xd0);
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reg32 &= ~(1 << 31);
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pci_write_config32(dev, 0xd0, reg32);
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/* Additional programming steps */
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reg32 = pci_read_config32(dev, 0xc4);
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reg32 |= (1 << 13);
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pci_write_config32(dev, 0xc4, reg32);
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reg32 = pci_read_config32(dev, 0xc4);
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reg32 |= (1 << 10);
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pci_write_config32(dev, 0xc4, reg32);
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reg32 = pci_read_config32(dev, 0xd0);
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reg32 &= ~(1 << 31);
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pci_write_config32(dev, 0xd0, reg32);
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/* Set Bus Master */
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reg32 = pci_read_config32(dev, PCI_COMMAND);
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pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
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pci_write_config8(dev, 0x3c, 0x0a); // unused?
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/* Codec Initialization Programming Sequence */
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reg32 = read32(base + 0x08);
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reg32 |= (1 << 0);
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write32(base + 0x08, reg32);
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//
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reg8 = pci_read_config8(dev, 0x40); // Audio Control
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reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb
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pci_write_config8(dev, 0x40, reg8);
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reg8 = pci_read_config8(dev, 0x4d); // Docking Status
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reg8 &= ~(1 << 7); // Docking not supported
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pci_write_config8(dev, 0x4d, reg8);
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codec_mask = codec_detect(base);
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if (codec_mask) {
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printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
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codecs_init(dev, base, codec_mask);
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}
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/* Enable dynamic clock gating */
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reg8 = pci_read_config8(dev, 0x43);
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reg8 &= ~0x7;
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reg8 |= (1 << 2) | (1 << 0);
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pci_write_config8(dev, 0x43, reg8);
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}
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static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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{
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if (!vendor || !device) {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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pci_read_config32(dev, PCI_VENDOR_ID));
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} else {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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}
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static struct pci_operations azalia_pci_ops = {
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.set_subsystem = azalia_set_subsystem,
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};
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static struct device_operations azalia_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = azalia_init,
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.scan_bus = 0,
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.ops_pci = &azalia_pci_ops,
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};
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static const unsigned short pci_device_ids[] = { 0x1c20, 0x1e20, 0 };
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static const struct pci_driver pch_azalia __pci_driver = {
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.ops = &azalia_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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