9a380abaa2
- Convert all PCI ID lists to new scheme - Unify code (variable names) - add missing PCI IDs for Panther Point PCIe root ports. Change-Id: I6357f6ebce7ddffe45a3ec642b0c594147f6134c Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1301 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
242 lines
7.1 KiB
C
242 lines
7.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include "pch.h"
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typedef struct southbridge_intel_bd82x6x_config config_t;
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static void sata_init(struct device *dev)
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{
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u32 reg32;
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u16 reg16;
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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printk(BIOS_DEBUG, "pch_sata: initializing...\n");
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if (config == NULL) {
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printk(BIOS_ERR, "pch_sata: error: device not in devicetree.cb!\n");
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return;
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}
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/* SATA configuration */
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/* Enable BARs */
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pci_write_config16(dev, PCI_COMMAND, 0x0007);
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if (config->ide_legacy_combined) {
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printk(BIOS_DEBUG, "SATA controller in combined mode.\n");
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/* No AHCI: clear AHCI base */
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pci_write_config32(dev, 0x24, 0x00000000);
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/* And without AHCI BAR no memory decoding */
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reg16 = pci_read_config16(dev, PCI_COMMAND);
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reg16 &= ~PCI_COMMAND_MEMORY;
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pci_write_config16(dev, PCI_COMMAND, reg16);
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pci_write_config8(dev, 0x09, 0x80);
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/* Set timings */
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pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
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IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
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pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
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IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
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IDE_PPE0 | IDE_IE0 | IDE_TIME0);
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/* Sync DMA */
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pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
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pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
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/* Set IDE I/O Configuration */
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reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
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pci_write_config32(dev, IDE_CONFIG, reg32);
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/* Port enable */
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reg16 = pci_read_config16(dev, 0x92);
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reg16 &= ~0x3f;
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reg16 |= config->sata_port_map;
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pci_write_config16(dev, 0x92, reg16);
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/* SATA Initialization register */
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pci_write_config32(dev, 0x94,
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((config->sata_port_map ^ 0x3f) << 24) | 0x183);
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} else if(config->sata_ahci) {
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u32 abar;
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printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n");
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/* Set Interrupt Line */
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/* Interrupt Pin is set by D31IP.PIP */
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pci_write_config8(dev, INTR_LN, 0x0a);
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/* Set timings */
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pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
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IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
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IDE_PPE0 | IDE_IE0 | IDE_TIME0);
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pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
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IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
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/* Sync DMA */
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pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
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pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
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/* Set IDE I/O Configuration */
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reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
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pci_write_config32(dev, IDE_CONFIG, reg32);
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/* for AHCI, Port Enable is managed in memory mapped space */
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reg16 = pci_read_config16(dev, 0x92);
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reg16 &= ~0x3f; /* 6 ports SKU + ORM */
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reg16 |= 0x8000 | config->sata_port_map;
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pci_write_config16(dev, 0x92, reg16);
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/* SATA Initialization register */
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pci_write_config32(dev, 0x94,
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((config->sata_port_map ^ 0x3f) << 24) | 0x183);
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/* Initialize AHCI memory-mapped space */
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abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
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printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
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/* CAP (HBA Capabilities) : enable power management */
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reg32 = read32(abar + 0x00);
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reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS
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reg32 &= ~0x00020060; // clear SXS+EMS+PMS
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write32(abar + 0x00, reg32);
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/* PI (Ports implemented) */
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write32(abar + 0x0c, config->sata_port_map);
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(void) read32(abar + 0x0c); /* Read back 1 */
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(void) read32(abar + 0x0c); /* Read back 2 */
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/* CAP2 (HBA Capabilities Extended)*/
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reg32 = read32(abar + 0x24);
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reg32 &= ~0x00000002;
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write32(abar + 0x24, reg32);
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/* VSP (Vendor Specific Register */
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reg32 = read32(abar + 0xa0);
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reg32 &= ~0x00000005;
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write32(abar + 0xa0, reg32);
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} else {
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printk(BIOS_DEBUG, "SATA controller in plain mode.\n");
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/* No AHCI: clear AHCI base */
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pci_write_config32(dev, 0x24, 0x00000000);
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/* And without AHCI BAR no memory decoding */
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reg16 = pci_read_config16(dev, PCI_COMMAND);
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reg16 &= ~PCI_COMMAND_MEMORY;
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pci_write_config16(dev, PCI_COMMAND, reg16);
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/* Native mode capable on both primary and secondary (0xa)
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* or'ed with enabled (0x50) = 0xf
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*/
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pci_write_config8(dev, 0x09, 0x8f);
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/* Set Interrupt Line */
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/* Interrupt Pin is set by D31IP.PIP */
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pci_write_config8(dev, INTR_LN, 0xff);
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/* Set timings */
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pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
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IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
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IDE_PPE0 | IDE_IE0 | IDE_TIME0);
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pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
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IDE_SITRE | IDE_ISP_3_CLOCKS |
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IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
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/* Sync DMA */
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pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
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pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
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/* Set IDE I/O Configuration */
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reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
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pci_write_config32(dev, IDE_CONFIG, reg32);
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/* Port enable */
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reg16 = pci_read_config16(dev, 0x92);
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reg16 &= ~0x3f;
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reg16 |= config->sata_port_map;
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pci_write_config16(dev, 0x92, reg16);
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/* SATA Initialization register */
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pci_write_config32(dev, 0x94,
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((config->sata_port_map ^ 0x3f) << 24) | 0x183);
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}
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}
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static void sata_enable(device_t dev)
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{
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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u16 map = 0;
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if (!config)
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return;
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/*
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* Set SATA controller mode early so the resource allocator can
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* properly assign IO/Memory resources for the controller.
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*/
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if (config->sata_ahci)
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map = 0x0060;
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map |= (config->sata_port_map ^ 0x3f) << 8;
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pci_write_config16(dev, 0x90, map);
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}
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static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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{
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if (!vendor || !device) {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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pci_read_config32(dev, PCI_VENDOR_ID));
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} else {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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}
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static struct pci_operations sata_pci_ops = {
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.set_subsystem = sata_set_subsystem,
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};
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static struct device_operations sata_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = sata_init,
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.enable = sata_enable,
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.scan_bus = 0,
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.ops_pci = &sata_pci_ops,
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};
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static const unsigned short pci_device_ids[] = { 0x1c00, 0x1c01, 0x1c02, 0x1c03,
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0x1e00, 0x1e01, 0x1e02, 0x1e03,
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0 };
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static const struct pci_driver pch_sata __pci_driver = {
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.ops = &sata_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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