99ac98f7e1
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the architecture specific to that stage i.e. we will have CONFIG_ARCH variables for each of the three stages. This allows us to have an SOC with any combination of architectures and thus every stage can be made to run on a completely different architecture independent of others. Thus, bootblock can have an x86 arch whereas romstage and ramstage can have arm32 and arm64 arch respectively. These stage specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain and compiler flags for every stage. These options can be considered as either arch or modes eg: x86 running in different modes or ARM having different arch types (v4, v7, v8). We have got rid of the original CONFIG_ARCH option completely as every stage can have any architecture of its own. Thus, almost all the components of coreboot are identified as being part of one of the three stages (bootblock, romstage or ramstage). The components which cannot be classified as such e.g. smm, rmodules can have their own compiler toolset which is for now set to *_i386. Hence, all special classes are treated in a similar way and the compiler toolset is defined using create_class_compiler defined in Makefile. In order to meet these requirements, changes have been made to CC, LD, OBJCOPY and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others. Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the toolsets are defined using create_class_compiler. Few additional macros have been introduced to identify the class to be used at various points, e.g.: CC_$(class) derives the $(class) part from the name of the stage being compiled. We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER as they do not make any sense for coreboot as a whole. All these attributes are associated with each of the stages. Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5577 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
430 lines
12 KiB
C
430 lines
12 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2003-2004 Eric Biederman
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* Copyright (C) 2005-2010 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <console/uart.h>
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#include <ip_checksum.h>
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#include <boot/coreboot_tables.h>
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#include <string.h>
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#include <version.h>
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#include <device/device.h>
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#include <stdlib.h>
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#include <cbfs.h>
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#include <cbmem.h>
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#include <bootmem.h>
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#if CONFIG_CHROMEOS
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#if CONFIG_GENERATE_ACPI_TABLES
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#include <arch/acpi.h>
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#endif
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <vendorcode/google/chromeos/gnvs.h>
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#endif
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#if CONFIG_ARCH_X86
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#include <cpu/x86/mtrr.h>
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#endif
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static struct lb_header *lb_table_init(unsigned long addr)
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{
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struct lb_header *header;
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/* 16 byte align the address */
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addr += 15;
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addr &= ~15;
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header = (void *)addr;
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header->signature[0] = 'L';
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header->signature[1] = 'B';
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header->signature[2] = 'I';
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header->signature[3] = 'O';
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header->header_bytes = sizeof(*header);
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header->header_checksum = 0;
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header->table_bytes = 0;
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header->table_checksum = 0;
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header->table_entries = 0;
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return header;
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}
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static struct lb_record *lb_first_record(struct lb_header *header)
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{
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struct lb_record *rec;
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rec = (void *)(((char *)header) + sizeof(*header));
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return rec;
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}
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static struct lb_record *lb_last_record(struct lb_header *header)
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{
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struct lb_record *rec;
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rec = (void *)(((char *)header) + sizeof(*header) + header->table_bytes);
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return rec;
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}
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static struct lb_record *lb_new_record(struct lb_header *header)
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{
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struct lb_record *rec;
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rec = lb_last_record(header);
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if (header->table_entries) {
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header->table_bytes += rec->size;
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}
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rec = lb_last_record(header);
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header->table_entries++;
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rec->tag = LB_TAG_UNUSED;
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rec->size = sizeof(*rec);
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return rec;
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}
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static struct lb_memory *lb_memory(struct lb_header *header)
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{
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struct lb_record *rec;
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struct lb_memory *mem;
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rec = lb_new_record(header);
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mem = (struct lb_memory *)rec;
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mem->tag = LB_TAG_MEMORY;
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mem->size = sizeof(*mem);
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return mem;
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}
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void lb_add_serial(struct lb_serial *new_serial, void *data)
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{
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struct lb_header *header = (struct lb_header *)data;
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struct lb_serial *serial;
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serial = (struct lb_serial *)lb_new_record(header);
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serial->tag = LB_TAG_SERIAL;
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serial->size = sizeof(*serial);
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serial->type = new_serial->type;
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serial->baseaddr = new_serial->baseaddr;
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serial->baud = new_serial->baud;
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}
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void lb_add_console(uint16_t consoletype, void *data)
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{
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struct lb_header *header = (struct lb_header *)data;
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struct lb_console *console;
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console = (struct lb_console *)lb_new_record(header);
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console->tag = LB_TAG_CONSOLE;
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console->size = sizeof(*console);
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console->type = consoletype;
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}
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static void lb_framebuffer(struct lb_header *header)
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{
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#if CONFIG_FRAMEBUFFER_KEEP_VESA_MODE || CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
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void fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
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int vbe_mode_info_valid(void);
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// If there isn't any mode info to put in the table, don't ask for it
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// to be filled with junk.
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if (!vbe_mode_info_valid())
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return;
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struct lb_framebuffer *framebuffer;
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framebuffer = (struct lb_framebuffer *)lb_new_record(header);
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fill_lb_framebuffer(framebuffer);
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framebuffer->tag = LB_TAG_FRAMEBUFFER;
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framebuffer->size = sizeof(*framebuffer);
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#endif
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}
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#if CONFIG_CHROMEOS
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void fill_lb_gpio(struct lb_gpio *gpio, int num,
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int polarity, const char *name, int value)
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{
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memset(gpio, 0, sizeof(*gpio));
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gpio->port = num;
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gpio->polarity = polarity;
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if (value >= 0)
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gpio->value = value;
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strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH);
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}
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static void lb_gpios(struct lb_header *header)
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{
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struct lb_gpios *gpios;
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gpios = (struct lb_gpios *)lb_new_record(header);
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gpios->tag = LB_TAG_GPIO;
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gpios->size = sizeof(*gpios);
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gpios->count = 0;
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fill_lb_gpios(gpios);
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}
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static void lb_vdat(struct lb_header *header)
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{
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#if CONFIG_GENERATE_ACPI_TABLES
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struct lb_vdat* vdat;
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vdat = (struct lb_vdat *)lb_new_record(header);
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vdat->tag = LB_TAG_VDAT;
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vdat->size = sizeof(*vdat);
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acpi_get_vdat_info(&vdat->vdat_addr, &vdat->vdat_size);
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#endif
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}
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static void lb_vbnv(struct lb_header *header)
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{
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#if CONFIG_PC80_SYSTEM
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struct lb_vbnv* vbnv;
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vbnv = (struct lb_vbnv *)lb_new_record(header);
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vbnv->tag = LB_TAG_VBNV;
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vbnv->size = sizeof(*vbnv);
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vbnv->vbnv_start = CONFIG_VBNV_OFFSET + 14;
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vbnv->vbnv_size = CONFIG_VBNV_SIZE;
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#endif
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}
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#if CONFIG_VBOOT_VERIFY_FIRMWARE
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static void lb_vboot_handoff(struct lb_header *header)
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{
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void *addr;
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uint32_t size;
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struct lb_vboot_handoff* vbho;
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if (vboot_get_handoff_info(&addr, &size))
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return;
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vbho = (struct lb_vboot_handoff *)lb_new_record(header);
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vbho->tag = LB_TAB_VBOOT_HANDOFF;
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vbho->size = sizeof(*vbho);
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vbho->vboot_handoff_addr = (intptr_t)addr;
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vbho->vboot_handoff_size = size;
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}
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#else
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static inline void lb_vboot_handoff(struct lb_header *header) {}
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#endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */
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#endif /* CONFIG_CHROMEOS */
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static void add_cbmem_pointers(struct lb_header *header)
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{
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/*
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* These CBMEM sections' addresses are included in the coreboot table
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* with the appropriate tags.
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*/
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const struct section_id {
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int cbmem_id;
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int table_tag;
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} section_ids[] = {
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{CBMEM_ID_TIMESTAMP, LB_TAG_TIMESTAMPS},
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{CBMEM_ID_CONSOLE, LB_TAG_CBMEM_CONSOLE},
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{CBMEM_ID_ACPI_GNVS, LB_TAG_ACPI_GNVS},
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};
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int i;
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for (i = 0; i < ARRAY_SIZE(section_ids); i++) {
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const struct section_id *sid = section_ids + i;
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struct lb_cbmem_ref *cbmem_ref;
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void *cbmem_addr = cbmem_find(sid->cbmem_id);
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if (!cbmem_addr)
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continue; /* This section is not present */
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cbmem_ref = (struct lb_cbmem_ref *)lb_new_record(header);
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if (!cbmem_ref) {
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printk(BIOS_ERR, "No more room in coreboot table!\n");
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break;
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}
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cbmem_ref->tag = sid->table_tag;
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cbmem_ref->size = sizeof(*cbmem_ref);
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cbmem_ref->cbmem_addr = (unsigned long)cbmem_addr;
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}
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}
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static struct lb_mainboard *lb_mainboard(struct lb_header *header)
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{
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struct lb_record *rec;
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struct lb_mainboard *mainboard;
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rec = lb_new_record(header);
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mainboard = (struct lb_mainboard *)rec;
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mainboard->tag = LB_TAG_MAINBOARD;
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mainboard->size = (sizeof(*mainboard) +
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strlen(mainboard_vendor) + 1 +
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strlen(mainboard_part_number) + 1 +
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3) & ~3;
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mainboard->vendor_idx = 0;
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mainboard->part_number_idx = strlen(mainboard_vendor) + 1;
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memcpy(mainboard->strings + mainboard->vendor_idx,
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mainboard_vendor, strlen(mainboard_vendor) + 1);
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memcpy(mainboard->strings + mainboard->part_number_idx,
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mainboard_part_number, strlen(mainboard_part_number) + 1);
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return mainboard;
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}
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static void lb_strings(struct lb_header *header)
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{
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static const struct {
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uint32_t tag;
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const char *string;
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} strings[] = {
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{ LB_TAG_VERSION, coreboot_version, },
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{ LB_TAG_EXTRA_VERSION, coreboot_extra_version, },
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{ LB_TAG_BUILD, coreboot_build, },
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{ LB_TAG_COMPILE_TIME, coreboot_compile_time, },
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{ LB_TAG_COMPILE_BY, coreboot_compile_by, },
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{ LB_TAG_COMPILE_HOST, coreboot_compile_host, },
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{ LB_TAG_COMPILE_DOMAIN, coreboot_compile_domain, },
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};
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unsigned int i;
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for(i = 0; i < ARRAY_SIZE(strings); i++) {
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struct lb_string *rec;
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size_t len;
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rec = (struct lb_string *)lb_new_record(header);
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len = strlen(strings[i].string);
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rec->tag = strings[i].tag;
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rec->size = (sizeof(*rec) + len + 1 + 3) & ~3;
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memcpy(rec->string, strings[i].string, len+1);
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}
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}
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static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header *next_header)
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{
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struct lb_record *rec;
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struct lb_forward *forward;
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rec = lb_new_record(header);
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forward = (struct lb_forward *)rec;
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forward->tag = LB_TAG_FORWARD;
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forward->size = sizeof(*forward);
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forward->forward = (uint64_t)(unsigned long)next_header;
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return forward;
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}
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static unsigned long lb_table_fini(struct lb_header *head)
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{
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struct lb_record *rec, *first_rec;
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rec = lb_last_record(head);
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if (head->table_entries) {
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head->table_bytes += rec->size;
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}
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first_rec = lb_first_record(head);
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head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes);
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head->header_checksum = 0;
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head->header_checksum = compute_ip_checksum(head, sizeof(*head));
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printk(BIOS_DEBUG,
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"Wrote coreboot table at: %p, 0x%x bytes, checksum %x\n",
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head, head->table_bytes, head->table_checksum);
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return (unsigned long)rec + rec->size;
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}
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unsigned long write_coreboot_table(
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unsigned long low_table_start, unsigned long low_table_end,
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unsigned long rom_table_start, unsigned long rom_table_end)
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{
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struct lb_header *head;
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if (low_table_start || low_table_end) {
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printk(BIOS_DEBUG, "Writing table forward entry at 0x%08lx\n",
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low_table_end);
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head = lb_table_init(low_table_end);
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lb_forward(head, (struct lb_header*)rom_table_end);
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low_table_end = (unsigned long) lb_table_fini(head);
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printk(BIOS_DEBUG, "Table forward entry ends at 0x%08lx.\n",
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low_table_end);
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low_table_end = ALIGN(low_table_end, 4096);
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printk(BIOS_DEBUG, "... aligned to 0x%08lx\n", low_table_end);
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}
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printk(BIOS_DEBUG, "Writing coreboot table at 0x%08lx\n",
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rom_table_end);
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head = lb_table_init(rom_table_end);
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rom_table_end = (unsigned long)head;
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printk(BIOS_DEBUG, "rom_table_end = 0x%08lx\n", rom_table_end);
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rom_table_end = ALIGN(rom_table_end, (64 * 1024));
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printk(BIOS_DEBUG, "... aligned to 0x%08lx\n", rom_table_end);
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#if CONFIG_USE_OPTION_TABLE
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{
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struct cmos_option_table *option_table = cbfs_get_file_content(
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CBFS_DEFAULT_MEDIA, "cmos_layout.bin",
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CBFS_COMPONENT_CMOS_LAYOUT, NULL);
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if (option_table) {
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struct lb_record *rec_dest = lb_new_record(head);
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/* Copy the option config table, it's already a lb_record... */
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memcpy(rec_dest, option_table, option_table->size);
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} else {
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printk(BIOS_ERR, "cmos_layout.bin could not be found!\n");
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}
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}
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#endif
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/* Initialize the memory map at boot time. */
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bootmem_init();
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if (low_table_start || low_table_end) {
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uint64_t size = low_table_end - low_table_start;
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/* Record the mptable and the the lb_table.
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* (This will be adjusted later) */
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bootmem_add_range(low_table_start, size, LB_MEM_TABLE);
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}
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/* Record the pirq table, acpi tables, and maybe the mptable. However,
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* these only need to be added when the rom_table is sitting below
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* 1MiB. If it isn't that means high tables are being written.
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* The code below handles high tables correctly. */
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if (rom_table_end <= (1 << 20)) {
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uint64_t size = rom_table_end - rom_table_start;
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bootmem_add_range(rom_table_start, size, LB_MEM_TABLE);
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}
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/* No other memory areas can be added after the memory table has been
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* committed as the entries won't show up in the serialize mem table. */
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bootmem_write_memory_table(lb_memory(head));
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/* Record our motherboard */
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lb_mainboard(head);
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/* Record the serial ports and consoles */
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#if CONFIG_CONSOLE_SERIAL
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uart_fill_lb(head);
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#endif
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#if CONFIG_CONSOLE_USB
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lb_add_console(LB_TAG_CONSOLE_EHCI, head);
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#endif
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/* Record our various random string information */
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lb_strings(head);
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/* Record our framebuffer */
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lb_framebuffer(head);
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#if CONFIG_CHROMEOS
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/* Record our GPIO settings (ChromeOS specific) */
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lb_gpios(head);
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/* pass along the VDAT buffer address */
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lb_vdat(head);
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/* pass along VBNV offsets in CMOS */
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lb_vbnv(head);
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/* pass along the vboot_handoff address. */
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lb_vboot_handoff(head);
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#endif
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add_cbmem_pointers(head);
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/* Remember where my valid memory ranges are */
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return lb_table_fini(head);
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}
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