4668ba77ea
The apollolake and skylake had duplicate stanzas of code for initializing the i2c buses. Additionally, they also had very similar structures for providing settings for the i2c speed control. Introduce a new struct lpss_i2c_bus_config and utilize it in both apollolake and skylake thereby removing the need for SoC-specific structres. The new structure is used for initializing a bus fully as the lpss i2c API is simplified in that lpss_i2c_init() is only required to be called. The struct lpss_i2c_bus_config structure is passed in for both initializing and filling in the SSDT information. The formerly exposed functions are made static to reduce the external API exposure. BUG=chrome-os-partner:58889 Change-Id: Ib4fa8a7a4de052da75c778a7658741a5a8e0e6b9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17348 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
104 lines
2.8 KiB
C
104 lines
2.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <commonlib/helpers.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/i2c.h>
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#include <device/pci_def.h>
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#include <soc/intel/common/lpss_i2c.h>
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#include <soc/i2c.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include "chip.h"
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static int i2c_early_init_bus(unsigned bus)
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{
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ROMSTAGE_CONST struct soc_intel_apollolake_config *config;
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ROMSTAGE_CONST struct device *tree_dev;
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pci_devfn_t dev;
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int devfn;
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uintptr_t base;
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uint32_t value;
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void *reg;
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/* Find the PCI device for this bus controller */
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devfn = i2c_bus_to_devfn(bus);
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if (devfn < 0) {
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printk(BIOS_ERR, "I2C%u device not found\n", bus);
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return -1;
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}
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/* Look up the controller device in the devicetree */
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dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn));
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tree_dev = dev_find_slot(0, devfn);
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if (!tree_dev || !tree_dev->enabled) {
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printk(BIOS_ERR, "I2C%u device not enabled\n", bus);
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return -1;
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}
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/* Skip if not enabled for early init */
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config = tree_dev->chip_info;
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if (!config || !config->i2c[bus].early_init) {
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printk(BIOS_ERR, "I2C%u not enabled for early init\n", bus);
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return -1;
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}
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/* Prepare early base address for access before memory */
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base = PRERAM_I2C_BASE_ADDRESS(bus);
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pci_write_config32(dev, PCI_BASE_ADDRESS_0, base);
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pci_write_config32(dev, PCI_COMMAND,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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/* Take device out of reset */
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reg = (void *)(base + I2C_LPSS_REG_RESET);
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value = read32(reg);
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value |= I2C_LPSS_RESET_RELEASE_HC;
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write32(reg, value);
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/* Initialize the controller */
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if (lpss_i2c_init(bus, &config->i2c[bus]) < 0) {
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printk(BIOS_ERR, "I2C%u failed to initialize\n", bus);
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return -1;
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}
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return 0;
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}
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uintptr_t lpss_i2c_base_address(unsigned bus)
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{
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unsigned devfn;
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pci_devfn_t dev;
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uintptr_t base;
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/* Find device+function for this controller */
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devfn = i2c_bus_to_devfn(bus);
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if (devfn < 0)
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return (uintptr_t)NULL;
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/* Form a PCI address for this device */
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dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn));
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/* Read the first base address for this device */
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base = ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16);
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/* Attempt to initialize bus if base is not set yet */
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if (!base && !i2c_early_init_bus(bus))
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base = ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0),
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16);
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return base;
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}
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