2871e0e78c
List of changes: 1. Add required SoC programming till ramstage 2. Include only required headers into include/soc 3. Add CPU, PCH and SA EDS document number and chapter number 4. Fill required FSP-S UPD to call FSP-S API Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
40 lines
1.3 KiB
C
40 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/pci_def.h>
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#include <intelblocks/cse.h>
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#include <intelblocks/smihandler.h>
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#include <soc/soc_chip.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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/*
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* Specific SOC SMI handler during ramstage finalize phase
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*
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* BIOS can't make CSME function disable as is due to POSTBOOT_SAI
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* restriction in place from ADP chipset. Hence create SMI Handler to
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* perform CSME function disabling logic during SMM mode.
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*/
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void smihandler_soc_at_finalize(void)
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{
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const struct soc_intel_alderlake_config *config;
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config = config_of_soc();
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if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM))
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heci_disable();
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}
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const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
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[SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
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[APM_STS_BIT] = smihandler_southbridge_apmc,
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[PM1_STS_BIT] = smihandler_southbridge_pm1,
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[GPE0_STS_BIT] = smihandler_southbridge_gpe0,
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[GPIO_STS_BIT] = smihandler_southbridge_gpi,
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[ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
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[MCSMI_STS_BIT] = smihandler_southbridge_mc,
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#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)
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[TCO_STS_BIT] = smihandler_southbridge_tco,
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#endif
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[PERIODIC_STS_BIT] = smihandler_southbridge_periodic,
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[MONITOR_STS_BIT] = smihandler_southbridge_monitor,
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};
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