3b0f20ba70
Change-Id: I99e5d7f3b46c90ca863ddf6c186b5447d0c8e6f2 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14607 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
26 lines
829 B
C
26 lines
829 B
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <device/pci_def.h>
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static void bootblock_southbridge_init(void)
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{
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uint32_t tmp;
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tmp = pci_read_config32(PCI_DEV(0, 7, 0), 0x40);
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/* decode all flash ranges */
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pci_write_config32(PCI_DEV(0, 7, 0), 0x40, tmp | 0x07ff0000);
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}
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