9a684fcb0f
Kconfigs from within the choice/endchoice block. This makes it possible to define user visible board specific options. Moved all vendor names and PCI ids to the vendors' Kconfigs. Now all options in each file depend on the same symbol, so replaced all "depends on"s with a single "if". Sorted boards (sort -d), cleaned whitespace. This patch also introduces a dummy option BOARD_SPECIFIC_OPTIONS, which is always "y" and never used. It it simply needed to have something to attach the boards' "select" statements to. Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
78 lines
1.2 KiB
Text
78 lines
1.2 KiB
Text
if BOARD_HP_DL145_G3
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select ARCH_X86
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select CPU_AMD_SOCKET_F
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select NORTHBRIDGE_AMD_AMDK8
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select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
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select SOUTHBRIDGE_BROADCOM_BCM21000
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select SOUTHBRIDGE_BROADCOM_BCM5785
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select SUPERIO_NSC_PC87417
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select HAVE_BUS_CONFIG
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select USE_DCACHE_RAM
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select HAVE_HARD_RESET
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select LIFT_BSP_APIC_ID
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select BOARD_ROMSIZE_KB_512
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select SB_HT_CHAIN_UNITID_OFFSET_ONLY
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config MAINBOARD_DIR
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string
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default hp/dl145_g3
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config DCACHE_RAM_BASE
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hex
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default 0xcc000
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config DCACHE_RAM_SIZE
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hex
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default 0x04000
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config DCACHE_RAM_GLOBAL_VAR_SIZE
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hex
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default 0x01000
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config APIC_ID_OFFSET
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hex
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default 0x8
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config SB_HT_CHAIN_ON_BUS0
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int
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default 2
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config MAINBOARD_PART_NUMBER
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string
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default "ProLiant DL145 G3"
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config HW_MEM_HOLE_SIZEK
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hex
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default 0x100000
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config MAX_CPUS
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int
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default 4
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config MAX_PHYSICAL_CPUS
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int
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default 2
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x1
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config HT_CHAIN_UNITID_BASE
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hex
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default 0x6
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config SB_HT_CHAIN_ON_BUS0
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int
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default 2
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config IRQ_SLOT_COUNT
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int
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default 15
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endif # BOARD_HP_DL145_G3
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