Michael Niewöhner 9abeb9c062 soc/intel/tgl: correct wrong gpio GPI enable register base offset ... Reference: Intel doc# 631120-001. Change-Id: Iaf3a1b7bc38a1b30f8cc901bd6496e77f2d92cfd Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>		2021-09-23 06:32:11 +00:00
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amd	soc/amd/common/block/gpio_banks: Rework GPIO pad configuration	2021-09-22 15:54:52 +00:00
cavium
example	src: Introduce ARCH_ALL_STAGES_X86	2021-07-02 08:19:10 +00:00
intel	soc/intel/tgl: correct wrong gpio GPI enable register base offset	2021-09-23 06:32:11 +00:00
mediatek	mipi: Make panel init callback work directly on DSI transaction types	2021-09-11 01:42:47 +00:00
nvidia	mipi: Make panel init callback work directly on DSI transaction types	2021-09-11 01:42:47 +00:00
qualcomm	soc/qualcomm/common: Move UART SC7180 driver to common section	2021-09-23 04:43:59 +00:00
rockchip	mipi: Make panel init callback work directly on DSI transaction types	2021-09-11 01:42:47 +00:00
samsung	commonlib/region: Turn addrspace_32bit into a more official API	2021-04-21 02:06:26 +00:00
sifive
ti	soc/ti/am335x/mmc.c: Fix memset length argument	2021-04-04 09:58:26 +00:00
ucb