Scott Duplichan 9b0c690c09 This patch corrects a coding error in the original implementation ... of 'Erratum 343 for AMD Fam10h CPUs' (rev 4345). The original code sets msr c001_102a bit 3 when bit 35 was intended. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5814 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1		2010-09-14 17:28:41 +00:00
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amd	This patch corrects a coding error in the original implementation	2010-09-14 17:28:41 +00:00
intel	We call this cache as ram everywhere, so let's call it the same in Kconfig	2010-08-30 17:53:13 +00:00
via	It should not be necessary to read in the rom during CAR setup.	2010-09-08 10:53:44 +00:00
x86	Adapt comment, too. (trivial)	2010-09-09 22:12:40 +00:00
Kconfig	We call this cache as ram everywhere, so let's call it the same in Kconfig	2010-08-30 17:53:13 +00:00
Makefile.inc	qemu: drop "northbridge.c" from src/cpu/...	2010-03-29 21:17:25 +00:00