9b4f221026
List of changes: 1. Add devicetree.cb config parameters related to FSP-S UPD 2. Configure GPIO as per ADL-P RVP 3. Add files required for ramstage(ec.c, mainboard.c) 4. Add smihandler.c for SMM 5. Add devicetree changes as below - USB OC PIN programing - GPE configuration - SATA port mapping - LPSS configuration - Audio configuration - IA common SoC configuration - EDP configuration - TCSS USB configuration - Enable S0ix TEST=Able to boot ADL-P RVP without Chrome EC (using on-board EC) with UART log over legacy UART0 port as 0x3f8 with NVME at RP9 reach till depthcharge payload. Change-Id: I120885956c88babfa09d24ce1079d49306919b8a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> |
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| .. | ||
| spd | ||
| variants | ||
| board_id.c | ||
| board_id.h | ||
| board_info.txt | ||
| bootblock.c | ||
| chromeos.c | ||
| chromeos.fmd | ||
| dsdt.asl | ||
| ec.c | ||
| Kconfig | ||
| Kconfig.name | ||
| mainboard.c | ||
| Makefile.inc | ||
| romstage_fsp_params.c | ||
| smihandler.c | ||