9bdb460a97
for paths - Renamed some configuration variables SMP -> CONFIG_SMP MAX_CPUS -> CONFIG_MAX_CPUS MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS - Removed some dead configuration variables MAX_CPUS -> CONFIG_MAX_CPUS MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS SMP -> CONFIG_SMP FINAL_MAINBOARD_FIXUP SIO_BASE SIO_SYSTEM_CLK_INPUT NO_KEYBOARD USE_NORMAL_IMAGE SERIAL_CONSOLE USE_ELF_BOOT ENABLE_FIXED_AND_VARIABLE_MTRRS START_CPU_SEG DISABLE_WATCHDOG ENABLE_IOMMU AMD8111_DEV - Removed some assembly files that are no longer needed killed src/southbridge/amd/amd8111/smbus.inc killed src/southbrideg/amd/amd8111/cmos_boot_failover.inc killed src/ram/ramtest.inc - Updates to config.g so that it works more reliably and has initial support for paths - Renamed some configuration variables SMP -> CONFIG_SMP MAX_CPUS -> CONFIG_MAX_CPUS MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS - Removed some dead configuration variables MAX_CPUS -> CONFIG_MAX_CPUS MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS SMP -> CONFIG_SMP FINAL_MAINBOARD_FIXUP SIO_BASE SIO_SYSTEM_CLK_INPUT NO_KEYBOARD USE_NORMAL_IMAGE SERIAL_CONSOLE USE_ELF_BOOT ENABLE_FIXED_AND_VARIABLE_MTRRS START_CPU_SEG DISABLE_WATCHDOG ENABLE_IOMMU AMD8111_DEV - Removed some assembly files that are no longer needed killed src/southbridge/amd/amd8111/smbus.inc killed src/southbrideg/amd/amd8111/cmos_boot_failover.inc killed src/ram/ramtest.inc killed src/sdram/generic_dump_spd.inc killed src/sdram/generic_dump_spd.inc - Updated the arima/hdama to build with the new configuration system - Updated config.g to list all of the variables with make echo git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
97 lines
1.9 KiB
Text
97 lines
1.9 KiB
Text
# Config file for Embedded Planet EP405PC board
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# This will make a target directory of ./ep405pc
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loadoptions
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target ep405pc
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uses ARCH
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uses CPU_OPT
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uses CROSS_COMPILE
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uses HAVE_OPTION_TABLE
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uses CONFIG_COMPRESS
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uses CONFIG_CHIP_CONFIGURE
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uses NO_POST
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uses CONFIG_IDE_STREAM
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uses CONFIG_SYS_CLK_FREQ
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uses IDE_BOOT_DRIVE
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uses IDE_SWAB IDE_OFFSET
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uses ROM_SIZE ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses _RESET
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uses _ROMBASE
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uses _RAMBASE
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uses CACHE_RAM_BASE
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uses CACHE_RAM_SIZE
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uses STACK_SIZE HEAP_SIZE
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uses MAINBOARD
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uses MAINBOARD_PART_NUMBER
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uses MAINBOARD_VENDOR
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## Enable PPC405 instructions
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option CPU_OPT="-Wa,-m405"
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## use a cross compiler
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option CROSS_COMPILE="powerpc-eabi-"
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## Use chip configuration
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option CONFIG_CHIP_CONFIGURE=1
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## We don't use compressed image
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option CONFIG_COMPRESS=0
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## Turn off POST codes
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option NO_POST=1
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## Boot linux from IDE
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option CONFIG_IDE_STREAM=1
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option IDE_BOOT_DRIVE=0
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option IDE_SWAB=1
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option IDE_OFFSET=0
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option ROM_SIZE=1048576
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## LinuxBIOS C code runs at this location in RAM
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option _RAMBASE=0x00100000
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## For the trick of using cache as ram
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## put the fake ram location at this address
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option CACHE_RAM_BASE=0x00200000
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option CACHE_RAM_SIZE=0x00004000
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##
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## Use a 64K stack
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##
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option STACK_SIZE=0x10000
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##
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## Use a 64K heap
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##
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option HEAP_SIZE=0x10000
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## Compute the location and size of where this firmware image
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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##
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option ROM_SECTION_SIZE=ROM_SIZE
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option ROM_SECTION_OFFSET=0
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##
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## System clock
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##
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option CONFIG_SYS_CLK_FREQ=33
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romimage "normal"
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## Reset vector address
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option _RESET=0xfffffffc
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## linuxBIOS ROM start address
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option _ROMBASE=0xfff00000
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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option ROM_IMAGE_SIZE=49152
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mainboard embeddedplanet/ep405pc
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end
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buildrom ROM_SIZE "normal"
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