coreboot-kgpe-d16/src/mainboard/google/poppy/dsdt.asl
Furquan Shaikh fc20ee43d7 mb/google/poppy: Add config option for camera ACPI support
This change adds a new config option VARIANT_HAS_CAMERA_ACPI to allow
variants to define ACPI tables for camera support. It also prevents
boards that do not need this from unnecessarily providing dummy files
for camera ACPI support.

Change-Id: I91f8e407e0f021071eeadbde8c2695e2a6d69e06
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-06 18:24:13 +00:00

77 lines
1.8 KiB
Text

/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <variant/ec.h>
#include <variant/gpio.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x05, // DSDT revision: ACPI v5.0
"COREv4", // OEM id
"COREBOOT", // OEM table id
0x20110725 // OEM revision
)
{
/* Some generic macros */
#include <soc/intel/skylake/acpi/platform.asl>
/* global NVS and variables */
#include <soc/intel/skylake/acpi/globalnvs.asl>
/* CPU */
#include <soc/intel/skylake/acpi/cpu.asl>
Scope (\_SB)
{
Device (PWRB)
{
Name (_HID, EisaId ("PNP0C0C"))
}
Device (PCI0)
{
/* Image processing unit */
#include <soc/intel/skylake/acpi/ipu.asl>
#include <soc/intel/skylake/acpi/systemagent.asl>
#include <soc/intel/skylake/acpi/pch.asl>
}
}
#if IS_ENABLED(CONFIG_VARIANT_HAS_CAMERA_ACPI)
/* Camera */
#include <variant/acpi/camera.asl>
#endif
/* Chrome OS specific */
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
#include <soc/intel/skylake/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
#include <ec/google/chromeec/acpi/superio.asl>
/* ACPI code for EC functions */
#include <ec/google/chromeec/acpi/ec.asl>
}
Scope (\_SB)
{
/* Dynamic Platform Thermal Framework */
#include <variant/acpi/dptf.asl>
}
}