6f32d80e18
Some LPC debug boards hard strap SIO address to be at 0x164e/0x164d vs 0x4e/0x4d. Add support for configurable SIO address to support these cards. BUG=b:159933344 TEST=boot with LPC debug card, verify serial output Change-Id: I103c61f21f13970dfa3b9a788b29964e478fb84c Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
24 lines
709 B
C
24 lines
709 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <amdblocks/lpc.h>
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#include <superio/smsc/sio1036/sio1036.h>
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#include "gpio.h"
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#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_ADDR_BASE, SIO1036_SP1)
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void bootblock_mainboard_early_init(void)
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{
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mainboard_program_early_gpios();
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if (CONFIG(SUPERIO_SMSC_SIO1036)) {
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if (CONFIG_SUPERIO_ADDR_BASE == 0x4e) {
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lpc_enable_sio_decode(LPC_SELECT_SIO_4E4F);
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} else {
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// set up 16 byte wide I/O range window for the super IO
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lpc_set_wideio_range(CONFIG_SUPERIO_ADDR_BASE & ~0xF, 16);
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}
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lpc_enable_decode(DECODE_ENABLE_SERIAL_PORT0 << CONFIG_UART_FOR_CONSOLE);
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sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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}
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