Felix Held 7608ea0c9f soc/amd/cezanne,common,picasso: use BERT region reserved by FSP driver ... commit ce0e2a0140 (drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region) adds a mechanism to reserve the BERT region inside the coreboot code, so we can get rid of the workaround to reserve it in the FSP and return the location in a HOB. mcfg->bert_size defaults to 0 which makes the FSP not generate the corresponding HOB, but that field is planned to be removed at least on Cezanne, so don't explicitly set it to 0. BUG=b:169934025 TEST=BERT table that gets generated in a follow-up patch for Picasso points to expected BERT region and Linux is able to access, decode and display it. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaca89b47793bf9982181560f026459a18e7db134 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52584 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-05-21 11:22:59 +00:00
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amd	soc/amd/cezanne,common,picasso: use BERT region reserved by FSP driver	2021-05-21 11:22:59 +00:00
cavium	src: use ARRAY_SIZE where possible	2021-02-15 11:30:40 +00:00
eltan	vc/eltan/security/mboot/Kconfig: Add dependency of VBOOT	2021-04-06 07:01:31 +00:00
google	mb/google: Move ECFW_RW setting for non-ChromeEC boards	2021-04-30 06:48:56 +00:00
intel	vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00	2021-05-16 22:17:26 +00:00
mediatek	vendor/mediatek: Add MT8195 dram initialization code	2021-05-14 04:00:38 +00:00
siemens	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
Makefile.inc	soc/mediatek/mt8192: initialize DRAM using vendor reference code	2021-03-08 03:15:43 +00:00