1d14b3e926
Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
101 lines
2.5 KiB
C
101 lines
2.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <console/console.h>
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#include <delay.h>
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#include <arch/io.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <soc/pch.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include <soc/spi.h>
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u8 pch_revision(void)
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{
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return pci_read_config8(PCH_DEV_LPC, PCI_REVISION_ID);
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}
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u16 pch_type(void)
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{
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return pci_read_config16(PCH_DEV_LPC, PCI_DEVICE_ID);
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}
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void *get_spi_bar(void)
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{
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device_t dev = PCH_DEV_SPI;
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uint32_t bar;
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bar = pci_read_config32(dev, PCH_SPI_BASE_ADDRESS);
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/* Bits 31-12 are the base address as per EDS for SPI 1F/5,
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* Don't care about 0-11 bit
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*/
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return (void *)(bar & ~(B_PCH_SPI_BAR0_MASK));
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}
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u32 pch_read_soft_strap(int id)
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{
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uint32_t fdoc;
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void *spibar = get_spi_bar();
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fdoc = read32(spibar + SPIBAR_FDOC);
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fdoc &= ~0x00007ffc;
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write32(spibar + SPIBAR_FDOC, fdoc);
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fdoc |= 0x00004000;
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fdoc |= id * 4;
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write32(spibar + SPIBAR_FDOC, fdoc);
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return read32(spibar + SPIBAR_FDOD);
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}
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#if ENV_RAMSTAGE
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void pch_enable_dev(device_t dev)
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{
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/* FSP should implement routines to disable PCH IPs */
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u32 reg32;
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/* These devices need special enable/disable handling */
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switch (PCI_SLOT(dev->path.pci.devfn)) {
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case PCH_DEV_SLOT_PCIE:
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return;
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}
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if (!dev->enabled) {
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printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
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/* Ensure memory, io, and bus master are all disabled */
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reg32 = pci_read_config32(dev, PCI_COMMAND);
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reg32 &= ~(PCI_COMMAND_MASTER |
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PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
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pci_write_config32(dev, PCI_COMMAND, reg32);
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/* Disable this device if possible */
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} else {
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/* Enable SERR */
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reg32 = pci_read_config32(dev, PCI_COMMAND);
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reg32 |= PCI_COMMAND_SERR;
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pci_write_config32(dev, PCI_COMMAND, reg32);
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}
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}
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#endif
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