coreboot-kgpe-d16/src/soc
Ben Gardner 2ae9cce87a intel/fsp_baytrail: use 20K PU/PD for GPIO
The E3800 datasheet only lists 2K and 20K Pull Strength for the GPIOs.
The 10K and 40K values map to 'reserved'.

This brings the code closer to the non-FSP baytrail.

Change-Id: I77078bdbbccc00976525dc43fb98f5b2e79eae03
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/13907
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-07 04:24:57 +01:00
..
broadcom/cygnus soc/*: fix uart's regwidth specification in cbtables 2016-02-21 12:26:05 +01:00
imgtec/pistachio urara: Increase bootblock size 2016-02-22 21:38:20 +01:00
intel intel/fsp_baytrail: use 20K PU/PD for GPIO 2016-03-07 04:24:57 +01:00
marvell soc/*: fix uart's regwidth specification in cbtables 2016-02-21 12:26:05 +01:00
mediatek/mt8173 soc/*: fix uart's regwidth specification in cbtables 2016-02-21 12:26:05 +01:00
nvidia soc/*: fix uart's regwidth specification in cbtables 2016-02-21 12:26:05 +01:00
qualcomm/ipq806x timestamp: Remove HAS_PRECBMEM_TIMESTAMP_REGION Kconfig 2016-02-12 21:54:52 +01:00
rockchip/rk3288 timestamp: Remove HAS_PRECBMEM_TIMESTAMP_REGION Kconfig 2016-02-12 21:54:52 +01:00
samsung soc/*: fix uart's regwidth specification in cbtables 2016-02-21 12:26:05 +01:00
ucb/riscv tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00