196 lines
5.3 KiB
C
196 lines
5.3 KiB
C
/*
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* inteltool - dump all registers on an Intel CPU + chipset based system.
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*
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* Copyright (C) 2008 by coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <stdio.h>
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#include "inteltool.h"
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static const io_register_t ich0_gpio_registers[] = {
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{ 0x00, 4, "GPIO_USE_SEL" },
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{ 0x04, 4, "GP_IO_SEL" },
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{ 0x08, 4, "RESERVED" },
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{ 0x0c, 4, "GP_LVL" },
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{ 0x10, 4, "RESERVED" },
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{ 0x14, 4, "GPO_TTL" },
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{ 0x18, 4, "GPO_BLINK" },
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{ 0x1c, 4, "RESERVED" },
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{ 0x20, 4, "RESERVED" },
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{ 0x24, 4, "RESERVED" },
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{ 0x28, 4, "RESERVED" },
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{ 0x2c, 4, "GPI_INV" },
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{ 0x30, 4, "RESERVED" },
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{ 0x34, 4, "RESERVED" },
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{ 0x38, 4, "RESERVED" },
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{ 0x3C, 4, "RESERVED" }
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};
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static const io_register_t ich4_gpio_registers[] = {
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{ 0x00, 4, "GPIO_USE_SEL" },
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{ 0x04, 4, "GP_IO_SEL" },
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{ 0x08, 4, "RESERVED" },
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{ 0x0c, 4, "GP_LVL" },
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{ 0x10, 4, "RESERVED" },
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{ 0x14, 4, "GPO_TTL" },
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{ 0x18, 4, "GPO_BLINK" },
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{ 0x1c, 4, "RESERVED" },
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{ 0x20, 4, "RESERVED" },
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{ 0x24, 4, "RESERVED" },
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{ 0x28, 4, "RESERVED" },
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{ 0x2c, 4, "GPI_INV" },
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{ 0x30, 4, "GPIO_USE_SEL2" },
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{ 0x34, 4, "GP_IO_SEL2" },
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{ 0x38, 4, "GP_LVL2" },
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{ 0x3C, 4, "RESERVED" }
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};
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static const io_register_t ich6_gpio_registers[] = {
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{ 0x00, 4, "GPIO_USE_SEL" },
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{ 0x08, 4, "RESERVED" },
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{ 0x0c, 4, "GP_LVL" },
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{ 0x10, 4, "RESERVED" },
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{ 0x14, 4, "RESERVED" },
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{ 0x18, 4, "GPO_BLINK" },
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{ 0x1c, 4, "RESERVED" },
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{ 0x20, 4, "RESERVED" },
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{ 0x24, 4, "RESERVED" },
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{ 0x28, 4, "RESERVED" },
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{ 0x2c, 4, "GPI_INV" },
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{ 0x30, 4, "GPIO_USE_SEL2" },
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{ 0x34, 4, "GP_IO_SEL2" },
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{ 0x38, 4, "GP_LVL2" },
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{ 0x04, 4, "GP_IO_SEL" },
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};
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static const io_register_t ich7_gpio_registers[] = {
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{ 0x00, 4, "GPIO_USE_SEL" },
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{ 0x04, 4, "GP_IO_SEL" },
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{ 0x08, 4, "RESERVED" },
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{ 0x0c, 4, "GP_LVL" },
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{ 0x10, 4, "RESERVED" },
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{ 0x14, 4, "RESERVED" },
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{ 0x18, 4, "GPO_BLINK" },
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{ 0x1c, 4, "RESERVED" },
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{ 0x20, 4, "RESERVED" },
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{ 0x24, 4, "RESERVED" },
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{ 0x28, 4, "RESERVED" },
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{ 0x2c, 4, "GPI_INV" },
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{ 0x30, 4, "GPIO_USE_SEL2" },
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{ 0x34, 4, "GP_IO_SEL2" },
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{ 0x38, 4, "GP_LVL2" },
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{ 0x3C, 4, "RESERVED" }
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};
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static const io_register_t ich8_gpio_registers[] = {
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{ 0x00, 4, "GPIO_USE_SEL" },
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{ 0x04, 4, "GP_IO_SEL" },
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{ 0x08, 4, "RESERVED" },
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{ 0x0c, 4, "GP_LVL" },
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{ 0x10, 4, "GPIO_USE_SEL Override (LOW)" },
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{ 0x14, 4, "RESERVED" },
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{ 0x18, 4, "GPO_BLINK" },
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{ 0x1c, 4, "GP_SER_BLINK" },
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{ 0x20, 4, "GP_SB_CMDSTS" },
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{ 0x24, 4, "GP_SB_DATA" },
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{ 0x28, 4, "RESERVED" },
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{ 0x2c, 4, "GPI_INV" },
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{ 0x30, 4, "GPIO_USE_SEL2" },
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{ 0x34, 4, "GP_IO_SEL2" },
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{ 0x38, 4, "GP_LVL2" },
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{ 0x3C, 4, "GPIO_USE_SEL Override (HIGH)" }
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};
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int print_gpios(struct pci_dev *sb)
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{
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int i, size;
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uint16_t gpiobase;
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const io_register_t *gpio_registers;
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printf("\n============= GPIOS =============\n\n");
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switch (sb->device_id) {
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case PCI_DEVICE_ID_INTEL_ICH8M:
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gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
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gpio_registers = ich8_gpio_registers;
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size = ARRAY_SIZE(ich8_gpio_registers);
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break;
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case PCI_DEVICE_ID_INTEL_ICH7:
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case PCI_DEVICE_ID_INTEL_ICH7M:
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case PCI_DEVICE_ID_INTEL_ICH7DH:
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case PCI_DEVICE_ID_INTEL_ICH7MDH:
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gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
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gpio_registers = ich7_gpio_registers;
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size = ARRAY_SIZE(ich7_gpio_registers);
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break;
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case PCI_DEVICE_ID_INTEL_ICH6:
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gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
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gpio_registers = ich6_gpio_registers;
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size = ARRAY_SIZE(ich6_gpio_registers);
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break;
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case PCI_DEVICE_ID_INTEL_ICH4:
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case PCI_DEVICE_ID_INTEL_ICH4M:
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gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
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gpio_registers = ich4_gpio_registers;
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size = ARRAY_SIZE(ich4_gpio_registers);
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break;
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case PCI_DEVICE_ID_INTEL_ICH:
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case PCI_DEVICE_ID_INTEL_ICH0:
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gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
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gpio_registers = ich0_gpio_registers;
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size = ARRAY_SIZE(ich0_gpio_registers);
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break;
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case PCI_DEVICE_ID_INTEL_82371XX:
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printf("This southbridge has GPIOs in the PM unit.\n");
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return 1;
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case 0x1234: // Dummy for non-existent functionality
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printf("This southbridge does not have GPIOBASE.\n");
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return 1;
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default:
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printf("Error: Dumping GPIOs on this southbridge is not (yet) supported.\n");
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return 1;
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}
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printf("GPIOBASE = 0x%04x (IO)\n\n", gpiobase);
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for (i = 0; i < size; i++) {
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switch (gpio_registers[i].size) {
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case 4:
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printf("gpiobase+0x%04x: 0x%08x (%s)\n",
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gpio_registers[i].addr,
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inl(gpiobase+gpio_registers[i].addr),
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gpio_registers[i].name);
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break;
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case 2:
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printf("gpiobase+0x%04x: 0x%04x (%s)\n",
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gpio_registers[i].addr,
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inw(gpiobase+gpio_registers[i].addr),
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gpio_registers[i].name);
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break;
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case 1:
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printf("gpiobase+0x%04x: 0x%02x (%s)\n",
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gpio_registers[i].addr,
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inb(gpiobase+gpio_registers[i].addr),
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gpio_registers[i].name);
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break;
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}
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}
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return 0;
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}
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