Mike Banon 8b7bda40f1 nb/amd/agesa: define DDR3_SPD_SIZE as a common value ... Move a size of DDR3 SPD memory (always 256 bytes) to a common define. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I80c89ff6e44526e1d75b0e933b21801ed17c98c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>		2020-08-24 09:18:12 +00:00
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amd	nb/amd/agesa: define DDR3_SPD_SIZE as a common value	2020-08-24 09:18:12 +00:00
cavium	vc/cavium: Fix up license headers	2020-07-28 10:54:58 +00:00
eltan	Kconfig: Escape variable to accommodate new Kconfig versions	2020-06-19 15:29:04 +00:00
google	vendorcode/google/chromeos: Introduce helper for CSE board reset	2020-08-22 00:31:34 +00:00
intel	edk2-stable202005/IntelFsp2Pkg: Add FSP*_ARCH_UPD.	2020-08-24 09:15:27 +00:00
siemens	src: Fix up ##-commented SPDX headers	2020-06-01 17:01:13 +00:00
Makefile.inc	vendorcode/eltan: Add vendor code for measured and verified boot	2019-06-04 10:41:53 +00:00