coreboot-kgpe-d16/src/northbridge
Patrick Georgi a0360af0f1 A couple of Poulsbo fixes:
- Don't include cmc.bin to the build. It's required, but we don't ship it
- mptable's API changes a bit. Adapt.
- Fix ACPI for new iasl versions with improved code validation

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-18 11:55:06 +00:00
..
amd Attached patch implements the memory speed reductions (and 2T/1T clock logic) for DDR1 memory (939 sockets). The details can be found in BKDG chapter 4.1.3.3. 2010-12-13 20:43:33 +00:00
intel A couple of Poulsbo fixes: 2010-12-18 11:55:06 +00:00
via drop one more version of doing serial uart output differently. 2010-12-17 00:08:21 +00:00
Kconfig Drop remainders of PPC port 2009-10-28 19:40:46 +00:00
Makefile.inc Drop remainders of PPC port 2009-10-28 19:40:46 +00:00