Felix Held a04400d1aa soc/amd/cezanne: add GPIO definitions ... Change-Id: I67930267a89ba0c64ec7e40e2bfa30a0618d104b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>		2020-12-17 14:48:50 +00:00
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include/soc	soc/amd/cezanne: add GPIO definitions	2020-12-17 14:48:50 +00:00
bootblock.c	soc/amd/cezanne: add caching setup in bootblock	2020-12-13 22:18:03 +00:00
chip.c	soc/amd/cezanne: add config.c and minimal chip.h	2020-12-06 19:05:47 +00:00
chip.h	soc/amd/cezanne: add config.c and minimal chip.h	2020-12-06 19:05:47 +00:00
config.c	soc/amd/cezanne: add config.c and minimal chip.h	2020-12-06 19:05:47 +00:00
early_fch.c	soc/amd/cezanne: add basic early FCH initialization to bootblock	2020-12-09 18:44:40 +00:00
Kconfig	soc/amd/cezanne: add 0xcf9 reset	2020-12-11 17:44:42 +00:00
Makefile.inc	soc/amd/cezanne: add caching setup in bootblock	2020-12-13 22:18:03 +00:00
reset.c	soc/amd/cezanne: add 0xcf9 reset	2020-12-11 17:44:42 +00:00
romstage.c