276 lines
9.9 KiB
C
276 lines
9.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef ELOG_H_
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#define ELOG_H_
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#include <compiler.h>
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/* SMI command code for GSMI event logging */
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#define ELOG_GSMI_APM_CNT 0xEF
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#define MAX_EVENT_SIZE 0x7F
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/* End of log */
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#define ELOG_TYPE_EOL 0xFF
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/*
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* Standard SMBIOS event log types below 0x80
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*/
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#define ELOG_TYPE_UNDEFINED_EVENT 0x00
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#define ELOG_TYPE_SINGLE_BIT_ECC_MEM_ERR 0x01
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#define ELOG_TYPE_MULTI_BIT_ECC_MEM_ERR 0x02
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#define ELOG_TYPE_MEM_PARITY_ERR 0x03
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#define ELOG_TYPE_BUS_TIMEOUT 0x04
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#define ELOG_TYPE_IO_CHECK 0x05
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#define ELOG_TYPE_SW_NMI 0x06
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#define ELOG_TYPE_POST_MEM_RESIZE 0x07
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#define ELOG_TYPE_POST_ERR 0x08
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#define ELOG_TYPE_PCI_PERR 0x09
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#define ELOG_TYPE_PCI_SERR 0x0A
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#define ELOG_TYPE_CPU_FAIL 0x0B
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#define ELOG_TYPE_EISA_TIMEOUT 0x0C
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#define ELOG_TYPE_CORRECTABLE_MEMLOG_DIS 0x0D
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#define ELOG_TYPE_LOG_DISABLED 0x0E
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#define ELOG_TYPE_UNDEFINED_EVENT2 0x0F
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#define ELOG_TYPE_SYS_LIMIT_EXCEED 0x10
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#define ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED 0x11
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#define ELOG_TYPE_SYS_CONFIG_INFO 0x12
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#define ELOG_TYPE_HDD_INFO 0x13
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#define ELOG_TYPE_SYS_RECONFIG 0x14
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#define ELOG_TYPE_CPU_ERROR 0x15
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#define ELOG_TYPE_LOG_CLEAR 0x16
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#define ELOG_TYPE_BOOT 0x17
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/*
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* Extended defined OEM event types start at 0x80
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*/
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/* OS/kernel events */
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#define ELOG_TYPE_OS_EVENT 0x81
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/* Last event from coreboot */
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#define ELOG_TYPE_OS_BOOT 0x90
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/* Embedded controller event */
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#define ELOG_TYPE_EC_EVENT 0x91
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#define EC_EVENT_LID_CLOSED 0x01
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#define EC_EVENT_LID_OPEN 0x02
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#define EC_EVENT_POWER_BUTTON 0x03
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#define EC_EVENT_AC_CONNECTED 0x04
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#define EC_EVENT_AC_DISCONNECTED 0x05
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#define EC_EVENT_BATTERY_LOW 0x06
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#define EC_EVENT_BATTERY_CRITICAL 0x07
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#define EC_EVENT_BATTERY 0x08
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#define EC_EVENT_THERMAL_THRESHOLD 0x09
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#define EC_EVENT_DEVICE_EVENT 0x0a
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#define EC_EVENT_THERMAL 0x0b
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#define EC_EVENT_USB_CHARGER 0x0c
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#define EC_EVENT_KEY_PRESSED 0x0d
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#define EC_EVENT_INTERFACE_READY 0x0e
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#define EC_EVENT_KEYBOARD_RECOVERY 0x0f
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#define EC_EVENT_THERMAL_SHUTDOWN 0x10
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#define EC_EVENT_BATTERY_SHUTDOWN 0x11
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#define EC_EVENT_FAN_ERROR 0x12
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#define EC_EVENT_THROTTLE_STOP 0x13
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#define EC_EVENT_HANG_DETECT 0x14
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#define EC_EVENT_HANG_REBOOT 0x15
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#define EC_EVENT_PD_MCU 0x16
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#define EC_EVENT_BATTERY_STATUS 0x17
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#define EC_EVENT_PANIC 0x18
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#define EC_EVENT_KEYBOARD_FASTBOOT 0x19
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#define EC_EVENT_RTC 0x1a
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#define EC_EVENT_MKBP 0x1b
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#define EC_EVENT_USB_MUX 0x1c
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#define EC_EVENT_MODE_CHANGE 0x1d
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#define EC_EVENT_KEYBOARD_RECOVERY_HWREINIT 0x1e
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#define EC_EVENT_EXTENDED 0x1f
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/* Power */
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#define ELOG_TYPE_POWER_FAIL 0x92
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#define ELOG_TYPE_SUS_POWER_FAIL 0x93
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#define ELOG_TYPE_PWROK_FAIL 0x94
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#define ELOG_TYPE_SYS_PWROK_FAIL 0x95
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#define ELOG_TYPE_POWER_ON 0x96
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#define ELOG_TYPE_POWER_BUTTON 0x97
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#define ELOG_TYPE_POWER_BUTTON_OVERRIDE 0x98
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/* Reset */
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#define ELOG_TYPE_RESET_BUTTON 0x99
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#define ELOG_TYPE_SYSTEM_RESET 0x9a
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#define ELOG_TYPE_RTC_RESET 0x9b
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#define ELOG_TYPE_TCO_RESET 0x9c
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/* Sleep/Wake */
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#define ELOG_TYPE_ACPI_ENTER 0x9d
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/* Deep Sx wake variant is provided below - 0xad */
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#define ELOG_TYPE_ACPI_WAKE 0x9e
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#define ELOG_TYPE_WAKE_SOURCE 0x9f
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#define ELOG_WAKE_SOURCE_PCIE 0x00
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#define ELOG_WAKE_SOURCE_PME 0x01
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#define ELOG_WAKE_SOURCE_PME_INTERNAL 0x02
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#define ELOG_WAKE_SOURCE_RTC 0x03
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#define ELOG_WAKE_SOURCE_GPIO 0x04
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#define ELOG_WAKE_SOURCE_SMBUS 0x05
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#define ELOG_WAKE_SOURCE_PWRBTN 0x06
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#define ELOG_WAKE_SOURCE_PME_HDA 0x07
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#define ELOG_WAKE_SOURCE_PME_GBE 0x08
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#define ELOG_WAKE_SOURCE_PME_EMMC 0x09
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#define ELOG_WAKE_SOURCE_PME_SDCARD 0x0a
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#define ELOG_WAKE_SOURCE_PME_PCIE1 0x0b
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#define ELOG_WAKE_SOURCE_PME_PCIE2 0x0c
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#define ELOG_WAKE_SOURCE_PME_PCIE3 0x0d
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#define ELOG_WAKE_SOURCE_PME_PCIE4 0x0e
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#define ELOG_WAKE_SOURCE_PME_PCIE5 0x0f
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#define ELOG_WAKE_SOURCE_PME_PCIE6 0x10
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#define ELOG_WAKE_SOURCE_PME_PCIE7 0x11
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#define ELOG_WAKE_SOURCE_PME_PCIE8 0x12
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#define ELOG_WAKE_SOURCE_PME_PCIE9 0x13
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#define ELOG_WAKE_SOURCE_PME_PCIE10 0x14
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#define ELOG_WAKE_SOURCE_PME_PCIE11 0x15
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#define ELOG_WAKE_SOURCE_PME_PCIE12 0x16
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#define ELOG_WAKE_SOURCE_PME_SATA 0x17
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#define ELOG_WAKE_SOURCE_PME_CSE 0x18
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#define ELOG_WAKE_SOURCE_PME_CSE2 0x19
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#define ELOG_WAKE_SOURCE_PME_CSE3 0x1a
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#define ELOG_WAKE_SOURCE_PME_XHCI 0x1b
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#define ELOG_WAKE_SOURCE_PME_XDCI 0x1c
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#define ELOG_WAKE_SOURCE_PME_XHCI_USB_2 0x1d
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#define ELOG_WAKE_SOURCE_PME_XHCI_USB_3 0x1e
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#define ELOG_WAKE_SOURCE_PME_WIFI 0x1f
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struct elog_event_data_wake {
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u8 source;
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u32 instance;
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} __packed;
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/* Chrome OS related events */
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#define ELOG_TYPE_CROS_DEVELOPER_MODE 0xa0
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#define ELOG_TYPE_CROS_RECOVERY_MODE 0xa1
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#define ELOG_CROS_RECOVERY_MODE_BUTTON 0x02
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/* Management Engine Events */
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#define ELOG_TYPE_MANAGEMENT_ENGINE 0xa2
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#define ELOG_TYPE_MANAGEMENT_ENGINE_EXT 0xa4
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struct elog_event_data_me_extended {
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u8 current_working_state;
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u8 operation_state;
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u8 operation_mode;
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u8 error_code;
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u8 progress_code;
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u8 current_pmevent;
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u8 current_state;
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} __packed;
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/* Last post code from previous boot */
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#define ELOG_TYPE_LAST_POST_CODE 0xa3
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#define ELOG_TYPE_POST_EXTRA 0xa6
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/* EC Shutdown Reason */
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#define ELOG_TYPE_EC_SHUTDOWN 0xa5
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/* ARM/generic versions of sleep/wake - These came from another firmware
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* apparently, but not all the firmware sources were updated so that the
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* elog namespace was coherent. */
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#define ELOG_TYPE_SLEEP 0xa7
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#define ELOG_TYPE_WAKE 0xa8
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#define ELOG_TYPE_FW_WAKE 0xa9
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/* Memory Cache Update */
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#define ELOG_TYPE_MEM_CACHE_UPDATE 0xaa
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#define ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL 0
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#define ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY 1
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#define ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE 2
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#define ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS 0
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#define ELOG_MEM_CACHE_UPDATE_STATUS_FAIL 1
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struct elog_event_mem_cache_update {
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u8 slot;
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u8 status;
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} __packed;
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/* CPU Thermal Trip */
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#define ELOG_TYPE_THERM_TRIP 0xab
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/* Cr50 */
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#define ELOG_TYPE_CR50_UPDATE 0xac
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/* Deep Sx wake variant */
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#define ELOG_TYPE_ACPI_DEEP_WAKE 0xad
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/* EC Device Event */
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#define ELOG_TYPE_EC_DEVICE_EVENT 0xae
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#define ELOG_EC_DEVICE_EVENT_TRACKPAD 0x01
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#define ELOG_EC_DEVICE_EVENT_DSP 0x02
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#define ELOG_EC_DEVICE_EVENT_WIFI 0x03
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/* S0ix sleep/wake */
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#define ELOG_TYPE_S0IX_ENTER 0xaf
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#define ELOG_TYPE_S0IX_EXIT 0xb0
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#if IS_ENABLED(CONFIG_ELOG)
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/* Eventlog backing storage must be initialized before calling elog_init(). */
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extern int elog_init(void);
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extern int elog_clear(void);
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/* Event addition functions return < 0 on failure and 0 on success. */
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extern int elog_add_event_raw(u8 event_type, void *data, u8 data_size);
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extern int elog_add_event(u8 event_type);
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extern int elog_add_event_byte(u8 event_type, u8 data);
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extern int elog_add_event_word(u8 event_type, u16 data);
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extern int elog_add_event_dword(u8 event_type, u32 data);
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extern int elog_add_event_wake(u8 source, u32 instance);
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extern int elog_smbios_write_type15(unsigned long *current, int handle);
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#else
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/* Stubs to help avoid littering sources with #if CONFIG_ELOG */
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static inline int elog_init(void) { return -1; }
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static inline int elog_clear(void) { return -1; }
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static inline int elog_add_event_raw(u8 event_type, void *data,
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u8 data_size) { return 0; }
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static inline int elog_add_event(u8 event_type) { return 0; }
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static inline int elog_add_event_byte(u8 event_type, u8 data) { return 0; }
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static inline int elog_add_event_word(u8 event_type, u16 data) { return 0; }
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static inline int elog_add_event_dword(u8 event_type, u32 data) { return 0; }
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static inline int elog_add_event_wake(u8 source, u32 instance) { return 0; }
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static inline int elog_smbios_write_type15(unsigned long *current,
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int handle) {
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return 0;
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}
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#endif
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extern u32 gsmi_exec(u8 command, u32 *param);
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#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
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u32 boot_count_read(void);
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#else
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static inline u32 boot_count_read(void)
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{
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return 0;
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}
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#endif
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u32 boot_count_increment(void);
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/*
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* Callback from GSMI handler to allow platform to log any wake source
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* information.
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*/
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void elog_gsmi_cb_platform_log_wake_source(void);
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/*
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* Callback from GSMI handler to allow mainboard to log any wake source
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* information.
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*/
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void elog_gsmi_cb_mainboard_log_wake_source(void);
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#endif /* ELOG_H_ */
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