6d6298dddc
Ability to choose compatibility mode is interesting for testing payloads and OS for compatibility with older systems. As per comments "ide_legacy_combined # TODO: Does nothing since generations, remove from sb code?" The "combined" mode was removed. It wasn't used by any mobo and the code for it is almost identical to IDE one other than few bits relating to interrupt handling and ISA mode. Change-Id: I407a8fac753b513812a86bef5abcf39c6d81472e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4658 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
82 lines
2.6 KiB
Text
82 lines
2.6 KiB
Text
chip northbridge/intel/sandybridge
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# Enable DisplayPort 1 Hotplug with 6ms pulse
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register "gpu_dp_d_hotplug" = "0x06"
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# Enable DisplayPort 0 Hotplug with 6ms pulse
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register "gpu_dp_c_hotplug" = "0x06"
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# Enable DVI Hotplug with 6ms pulse
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register "gpu_dp_b_hotplug" = "0x06"
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device cpu_cluster 0 on
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chip cpu/intel/socket_rPGA989
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device lapic 0 on end
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end
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chip cpu/intel/model_206ax
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# Magic APIC ID to locate this chip
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device lapic 0xACAC off end
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register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3)
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register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6)
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register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
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register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3)
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register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6)
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register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
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end
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end
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device domain 0 on
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device pci 00.0 on end # host bridge
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device pci 02.0 on end # vga controller
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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register "pirqa_routing" = "0x8b"
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register "pirqb_routing" = "0x8a"
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register "pirqc_routing" = "0x8b"
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register "pirqd_routing" = "0x8b"
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register "pirqe_routing" = "0x80"
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register "pirqf_routing" = "0x80"
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register "pirqg_routing" = "0x80"
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register "pirqh_routing" = "0x80"
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# GPI routing
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# 0 No effect (default)
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# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
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# 2 SCI (if corresponding GPIO_EN bit is also set)
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register "gpi1_routing" = "1"
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register "gpi14_routing" = "2"
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register "alt_gp_smi_en" = "0x0002"
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register "gpe0_en" = "0x4000"
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register "sata_port_map" = "0x3f"
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# SuperIO range is 0x700-0x73f
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register "gen2_dec" = "0x003c0701"
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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device pci 19.0 off end # Intel Gigabit Ethernet
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device pci 1a.0 on end # USB2 EHCI #2
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device pci 1b.0 on end # High Definition Audio
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device pci 1c.0 on end # PCIe Port #1 (WLAN)
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device pci 1c.1 off end # PCIe Port #2
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device pci 1c.2 on end # PCIe Port #3 (Debug)
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device pci 1c.3 on end # PCIe Port #4 (LAN)
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device pci 1c.4 off end # PCIe Port #5
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device pci 1c.5 off end # PCIe Port #6
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device pci 1c.6 off end # PCIe Port #7
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device pci 1c.7 off end # PCIe Port #8
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device pci 1d.0 on end # USB2 EHCI #1
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on end # LPC bridge
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device pci 1f.2 on end # SATA Controller 1
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device pci 1f.3 on end # SMBus
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device pci 1f.5 off end # SATA Controller 2
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device pci 1f.6 on end # Thermal
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end
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end
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end
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