coreboot-kgpe-d16/src/mainboard/google/urara
Ionela Voinescu 33c10f8c32 urara: Configure UART line control to 8N1
8bit, 1 stop bit, no parity

BUG=chrome-os-partner:31438
TEST=built urara bootblock and ran it on the Pistachio FPGA, observed
      expected console output.
BRANCH=none

Change-Id: Iface623f0b267f851e6d162d0321d56e3713a785
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 4122ae983dba907c10d0d0980863ae7bf94eda5e
Original-Change-Id: I14fe343c98b11774b93b2724b6bffa3b45ea17b4
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/226551
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9185
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-02 21:46:13 +02:00
..
devicetree.cb urara: use proper SOC name 2015-03-27 08:06:26 +01:00
Kconfig urara: Configure UART line control to 8N1 2015-04-02 21:46:13 +02:00
mainboard.c urara: use proper SOC name 2015-03-27 08:06:26 +01:00
Makefile.inc urara: introduce board skeleton 2015-03-27 08:06:24 +01:00