4cf5ecf39d
Intel 810 chipset (and all boards using it). This isn't required for this chipset as there's only one memory controller. This also helps a lot with romcc register usage, you should see the dreaded "too few registers" less often. Build-tested with all three boards using the Intel 810 chipset. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
67 lines
2 KiB
C
67 lines
2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define ASSEMBLY 1
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#include <stdint.h>
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#include <stdlib.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <arch/hlt.h>
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
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#include "northbridge/intel/i82810/raminit.h"
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#include "lib/debug.c"
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#include "pc80/udelay_io.c"
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#include "lib/delay.c"
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#include "cpu/x86/mtrr/earlymtrr.c"
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#include "cpu/x86/bist.h"
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#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
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#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
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static inline int spd_read_byte(unsigned int device, unsigned int address)
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{
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return smbus_read_byte(device, address);
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}
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#include "northbridge/intel/i82810/raminit.c"
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/* #include "northbridge/intel/i82810/debug.c" */
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static void main(unsigned long bist)
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{
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if (bist == 0)
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early_mtrr_init();
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smscsuperio_enable_serial(SERIAL_DEV, TTYS0_BASE);
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uart_init();
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console_init();
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report_bist_failure(bist);
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enable_smbus();
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/* dump_spd_registers(); */
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sdram_set_registers();
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sdram_set_spd_registers();
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sdram_enable();
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/* ram_check(0, 640 * 1024); */
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}
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