beb12880a1
Add the basics for building as a ChromeOS device. ChromeOS and ChromeEC are dependent on each other, so bring them in together. The EC is a Nuvoton and you can find additional details in the Chromium EC repo. Add the Google HWID "Kahlee TEST 6421". The chromeos.fmd for Kahlee takes advantage of the AGESA located outside cbfs and includes typical RW, VPD, and MRC areas. There are some updates required to depthcharge, vboot, GPIOs, and the ChromeEC before we have a complete-ish system. Change-Id: Ifb0a6afc01dd80ef9e7bb81039d9152936043999 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
97 lines
3.7 KiB
C
97 lines
3.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <arch/acpi.h>
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#include <agesawrapper.h>
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#include <amd_pci_util.h>
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#include <ec.h>
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/***********************************************************
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* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
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* This table is responsible for physically routing the PIC and
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* IOAPIC IRQs to the different PCI devices on the system. It
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* is read and written via registers 0xC00/0xC01 as an
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* Index/Data pair. These values are chipset and mainboard
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* dependent and should be updated accordingly.
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*
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* These values are used by the PCI configuration space,
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* MP Tables. TODO: Make ACPI use these values too.
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*/
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const u8 mainboard_picr_data[] = {
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[0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F,
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[0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
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[0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F,
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[0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
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[0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05,
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[0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x40] = 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F,
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[0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
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[0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
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[0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
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[0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F,
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[0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
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};
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const u8 mainboard_intr_data[] = {
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[0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
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[0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
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[0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10,
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[0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
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[0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00,
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[0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00,
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[0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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[0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F,
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[0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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};
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/* PIRQ Setup */
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static void pirq_setup(void)
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{
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intr_data_ptr = mainboard_intr_data;
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picr_data_ptr = mainboard_picr_data;
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}
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/*************************************************
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* Dedicated mainboard function
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*************************************************/
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static void kahlee_enable(device_t dev)
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{
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printk(BIOS_INFO, "Mainboard "
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CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
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/* Initialize the PIRQ data structures for consumption */
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pirq_setup();
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mainboard_ec_init();
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}
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struct chip_operations mainboard_ops = {
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.enable_dev = kahlee_enable,
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};
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