a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
236 lines
6.1 KiB
C
236 lines
6.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include <soc/sata.h>
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#include <console/console.h>
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#include <delay.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include "chip.h"
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typedef struct soc_intel_baytrail_config config_t;
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static inline void sir_write(struct device *dev, int idx, u32 value)
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{
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pci_write_config32(dev, SATA_SIRI, idx);
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pci_write_config32(dev, SATA_SIRD, value);
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}
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static void sata_init(struct device *dev)
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{
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config_t *config = dev->chip_info;
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u32 reg32;
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u16 reg16;
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u8 reg8;
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printk(BIOS_DEBUG, "SATA: Initializing...\n");
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if (config == NULL) {
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printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n");
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return;
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}
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if (!config->sata_ahci) {
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/* Set legacy or native decoding mode */
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if (config->ide_legacy_combined) {
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reg8 = pci_read_config8(dev, 0x09);
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reg8 &= ~0x5;
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pci_write_config8(dev, 0x09, reg8);
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} else {
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reg8 = pci_read_config8(dev, 0x09);
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reg8 |= 0x5;
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pci_write_config8(dev, 0x09, reg8);
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}
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/* Set capabilities pointer */
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pci_write_config8(dev, 0x34, 0x70);
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reg16 = pci_read_config16(dev, 0x70);
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reg16 &= ~0xFF00;
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pci_write_config16(dev, 0x70, reg16);
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}
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/* Primary timing - decode enable */
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reg16 = pci_read_config16(dev, 0x40);
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reg16 |= 1 << 15;
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pci_write_config16(dev, 0x40, reg16);
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/* Secondary timing - decode enable */
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reg16 = pci_read_config16(dev, 0x42);
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reg16 |= 1 << 15;
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pci_write_config16(dev, 0x42, reg16);
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/* Port mapping enables */
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reg16 = pci_read_config16(dev, 0x90);
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reg16 |= (config->sata_port_map ^ 0x3) << 8;
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pci_write_config16(dev, 0x90, reg16);
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/* Port control enables */
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reg16 = pci_read_config16(dev, 0x92);
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reg16 &= ~0x003f;
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reg16 |= config->sata_port_map;
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pci_write_config16(dev, 0x92, reg16);
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if (config->sata_ahci) {
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u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
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/* Enable CR memory space decoding */
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reg16 = pci_read_config16(dev, 0x04);
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reg16 |= 0x2;
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pci_write_config16(dev, 0x04, reg16);
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/* Set capability register */
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reg32 = read32(abar + 0x00);
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reg32 |= 0x0c046000; // set PSC+SSC+SALP+SSS+SAM
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reg32 &= ~0x00f20060; // clear SXS+EMS+PMS+gen bits
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reg32 |= (0x3 << 20); // Gen3 SATA
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write32(abar + 0x00, reg32);
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/* Ports enabled */
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reg32 = read32(abar + 0x0c);
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reg32 &= (u32)(~0x3f);
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reg32 |= config->sata_port_map;
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write32(abar + 0xc, reg32);
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/* Two extra reads to latch */
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read32(abar + 0x0c);
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read32(abar + 0x0c);
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/* Set cap2 - Support devslp */
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reg32 = (1 << 5) | (1 << 4) | (1 << 3);
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write32(abar + 0x24, reg32);
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/* Set PxCMD registers */
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reg32 = read32(abar + 0x118);
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reg32 &= ~((1 << 27) | (1 << 26) | (1 << 22) | (1 << 21) |
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(1 << 19) | (1 << 18) | (1 << 1));
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reg32 |= 2;
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write32(abar + 0x118, reg32);
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reg32 = read32(abar + 0x198);
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reg32 &= ~((1 << 27) | (1 << 26) | (1 << 22) | (1 << 21) |
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(1 << 19) | (1 << 18) | (1 << 1));
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reg32 |= 2;
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write32(abar + 0x198, reg32);
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/* Clear reset features */
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write32(abar + 0xc8, 0);
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/* Enable interrupts */
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reg8 = read8(abar + 0x04);
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reg8 |= 0x02;
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write8(abar + 0x04, reg8);
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} else {
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/* TODO(shawnn): Configure IDE SATA speed regs */
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}
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/* 1.4 us delay after configuring port / enable bits */
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udelay(2);
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/* Enable clock for ports */
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reg32 = pci_read_config32(dev, 0x94);
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reg32 |= 0x3f << 24;
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pci_write_config32(dev, 0x94, reg32);
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reg32 &= (config->sata_port_map ^ 0x3) << 24;
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pci_write_config32(dev, 0x94, reg32);
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/* Lock SataGc register */
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reg32 = (0x1 << 31) | (0x7 << 12);
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pci_write_config32(dev, 0x98, reg32);
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}
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static void sata_enable(device_t dev)
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{
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config_t *config = dev->chip_info;
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u8 reg8;
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u16 reg16;
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u32 reg32;
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southcluster_enable_dev(dev);
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if (!config)
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return;
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/* Port mapping -- mask off SPD + SMS + SC bits, then re-set */
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reg16 = pci_read_config16(dev, 0x90);
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reg16 &= ~0x03e0;
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reg16 |= (config->sata_port_map ^ 0x3) << 8;
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if(config->sata_ahci)
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reg16 |= 0x60;
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pci_write_config16(dev, 0x90, reg16);
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/* Set reg 0x94 before starting configuration */
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reg32 = pci_read_config32(dev, 0x94);
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reg32 &= (u32)(~0x1ff);
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reg32 |= 0x183;
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pci_write_config32(dev, 0x94, reg32);
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/* Set ORM bit */
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reg16 = pci_read_config16(dev, 0x92);
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reg16 |= (1 << 15);
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pci_write_config16(dev, 0x92, reg16);
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/* R_PCH_SATA_TM2 - Undocumented in EDS, set according to ref. code */
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reg32 = pci_read_config32(dev, 0x98);
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reg32 &= (u32)~(0x1f80 | (1 << 6) | (1 << 5));
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reg32 |= (1 << 29) | (1 << 25) | (1 << 23) | (1 << 22) |
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(1 << 20) | (1 << 19) | (1 << 18) | (1 << 9) | (1 << 5);
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pci_write_config32(dev, 0x98, reg32);
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/* CMD reg - set bus master enable (BME) */
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reg8 = pci_read_config8(dev, 0x04);
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reg8 |= (1 << 2);
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pci_write_config8(dev, 0x04, reg8);
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/* "Test mode registers" */
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sir_write(dev, 0x70, 0x00288301);
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sir_write(dev, 0x54, 0x00000300);
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sir_write(dev, 0x58, 0x50000000);
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/* "OOB Detection Margin */
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sir_write(dev, 0x6c, 0x130C0603);
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/* "Gasket Control" */
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sir_write(dev, 0xf4, 0);
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/* PCS - Enable requested SATA ports */
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reg8 = pci_read_config8(dev, 0x92);
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reg8 &= ~0x03;
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reg8 |= config->sata_port_map;
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pci_write_config8(dev, 0x92, reg8);
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}
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static struct device_operations sata_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = sata_init,
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.enable = sata_enable,
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.scan_bus = NULL,
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.ops_pci = &soc_pci_ops,
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};
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static const unsigned short pci_device_ids[] = {
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IDE1_DEVID, IDE2_DEVID, /* IDE */
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AHCI1_DEVID, AHCI2_DEVID, /* AHCI */
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0,
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};
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static const struct pci_driver baytrail_sata __pci_driver = {
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.ops = &sata_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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