coreboot-kgpe-d16/src/soc/intel/skylake/uart_debug.c
Subrata Banik 7e9cb92815 soc/intel/skylake: Add support for all UART port index
Select LPSS UART Base address based on LPSS UART port index.

Change-Id: I306d3d299f8d6a890ae519c74008f9d0d9dd1a76
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-21 16:29:55 +00:00

26 lines
812 B
C

/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stddef.h>
#include <console/uart.h>
#include <soc/iomap.h>
#include <soc/serialio.h>
uintptr_t uart_platform_base(int idx)
{
/* Same base address for all debug port usage. In reality UART2
* is currently only supported. */
return UART_BASE_0_ADDR(idx);
}