6f55154cd7
For boards with cimx/sb800, mainboards defined only empty stubs. Reset functionality is handled as BiosCallout. For amd/inagua, the defined function was actually initial GPIO programming. For cimx/sb700, function had prototypes but no callers. For cimx/sb900, everything was commented out already. Change-Id: I936feb4fc41d903078620c919a733bb9f39c3efb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
300 lines
10 KiB
C
300 lines
10 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <device/pci_def.h>
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#include <southbridge/amd/common/amd_pci_util.h>
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#include <southbridge/amd/cimx/cimx_util.h>
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#include <arch/acpi.h>
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#include <smbios.h>
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#include <string.h>
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#include "SBPLATFORM.h"
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#include <southbridge/amd/cimx/sb800/pci_devs.h>
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#include <northbridge/amd/agesa/family14/pci_devs.h>
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#include <superio/nuvoton/nct5104d/nct5104d.h>
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#include "gpio_ftns.h"
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/***********************************************************
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* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
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* This table is responsible for physically routing the PIC and
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* IOAPIC IRQs to the different PCI devices on the system. It
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* is read and written via registers 0xC00/0xC01 as an
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* Index/Data pair. These values are chipset and mainboard
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* dependent and should be updated accordingly.
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*
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* These values are used by the PCI configuration space,
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* MP Tables. TODO: Make ACPI use these values too.
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*
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* The PCI INTA/B/C/D pins are connected to
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* FCH pins INTE/F/G/H on the schematic so these need
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* to be routed as well.
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*/
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static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
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/* INTA# - INTH# */
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[0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
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/* Misc-nil,0,1,2, INT from Serial irq */
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[0x08] = 0x00,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
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/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */
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[0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F,
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/* IMC INT0 - 5 */
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[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
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/* USB Devs 18/19/20/22 INTA-C */
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[0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,
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/* IDE, SATA */
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[0x40] = 0x0B,0x0B,
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/* GPPInt0 - 3 */
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[0x50] = 0x0A,0x0B,0x0A,0x0B
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};
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static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
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/* INTA# - INTH# */
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[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
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/* Misc-nil,0,1,2, INT from Serial irq */
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[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
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/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */
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[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,
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/* IMC INT0 - 5 */
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[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
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/* USB Devs 18/19/22/20 INTA-C */
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[0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,
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/* IDE, SATA */
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[0x40] = 0x11,0x13,
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/* GPPInt0 - 3 */
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[0x50] = 0x10,0x11,0x12,0x13
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};
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/*
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* This table defines the index into the picr/intr_data
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* tables for each device. Any enabled device and slot
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* that uses hardware interrupts should have an entry
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* in this table to define its index into the FCH
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* PCI_INTR register 0xC00/0xC01. This index will define
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* the interrupt that it should use. Putting PIRQ_A into
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* the PIN A index for a device will tell that device to
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* use PIC IRQ 10 if it uses PIN A for its hardware INT.
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*/
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/*
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* The PCI slot INTA/B/C/D connected to PIRQE/F/G/H
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* but because of PCI INT_PIN swizzle isnt implemented to match
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* the IDSEL (dev 3) of the slot, the table is adjusted for the
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* swizzle and INTA is connected to PIRQH so PINA/B/C/D on
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* off-chip devices should get mapped to PIRQH/E/F/G.
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*/
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static const struct pirq_struct mainboard_pirq_data[] = {
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/* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */
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{GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */
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{NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 04.0 */
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{NB_PCIE_PORT2_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 05.0 */
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{NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 06.0 */
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{NB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* miniPCIe: 07.0 */
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{SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */
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{OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */
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{EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */
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{OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */
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{EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */
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{SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */
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{IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */
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{HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */
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{SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI bdg: 14.4 */
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{OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */
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{SB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* miniPCIe: 15.0 */
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{OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */
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{EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */
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};
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/* PIRQ Setup */
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static void pirq_setup(void)
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{
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pirq_data_ptr = mainboard_pirq_data;
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pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct);
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intr_data_ptr = mainboard_intr_data;
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picr_data_ptr = mainboard_picr_data;
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}
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/* Wrapper to enable GPIO/UART devices under menuconfig. Revisit
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* once configuration file format for SPI flash storage is complete.
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*/
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#define SIO_PORT 0x2e
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static void config_gpio_mux(void)
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{
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struct device *uart, *gpio;
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uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3);
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gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0);
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if (uart)
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uart->enabled = CONFIG_APU1_PINMUX_UART_C;
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if (gpio)
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gpio->enabled = CONFIG_APU1_PINMUX_GPIO0;
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uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4);
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gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1);
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if (uart)
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uart->enabled = CONFIG_APU1_PINMUX_UART_D;
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if (gpio)
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gpio->enabled = CONFIG_APU1_PINMUX_GPIO1;
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}
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static void pnp_raw_resource(struct device *dev, u8 reg, u8 val)
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{
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struct resource *res;
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res = new_resource(dev, reg);
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res->base = val;
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res->size = 0;
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res->flags |= IORESOURCE_IRQ | IORESOURCE_ASSIGNED;
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}
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static void config_addon_uart(void)
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{
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struct device *uart;
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uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3);
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if (uart && uart->enabled && CONFIG_UART_C_RS485)
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pnp_raw_resource(uart, 0xf2, 0x12);
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uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4);
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if (uart && uart->enabled && CONFIG_UART_D_RS485)
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pnp_raw_resource(uart, 0xf2, 0x12);
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}
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/**********************************************
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* Enable the dedicated functions of the board.
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**********************************************/
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static void mainboard_enable(device_t dev)
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{
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printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
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config_gpio_mux();
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config_addon_uart();
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/* Power off unused clock pins of GPP PCIe devices */
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u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
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/* GPP CLK0-2 are connected to the 3 ethernet chips
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* GPP CLK3-4 are connected to the miniPCIe slots */
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write8(misc_mem_clk_cntrl + 0, 0x21);
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write8(misc_mem_clk_cntrl + 1, 0x43);
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/* GPP CLK5 is only connected to test pads -> disable */
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write8(misc_mem_clk_cntrl + 2, 0x05);
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/* disable unconnected GPP CLK6-8 and SLT_GFX_CLK */
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write8(misc_mem_clk_cntrl + 3, 0x00);
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write8(misc_mem_clk_cntrl + 4, 0x00);
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/* Initialize the PIRQ data structures for consumption */
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pirq_setup();
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}
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/*
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* We will stuff a modified version of the first NICs (BDF 1:0.0) MAC address
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* into the smbios serial number location.
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*/
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const char *smbios_mainboard_serial_number(void)
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{
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static char serial[10];
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device_t nic_dev;
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uintptr_t bar18;
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u32 mac_addr = 0;
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int i;
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nic_dev = dev_find_slot(1, PCI_DEVFN(0, 0));
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if ((serial[0] != 0) || !nic_dev)
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return serial;
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/* Read in the last 3 bytes of NIC's MAC address. */
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bar18 = pci_read_config32(nic_dev, 0x18);
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bar18 &= 0xFFFFFC00;
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for (i = 3; i < 6; i++) {
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mac_addr <<= 8;
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mac_addr |= read8((u8 *)bar18 + i);
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}
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mac_addr &= 0x00FFFFFF;
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mac_addr /= 4;
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mac_addr -= 64;
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snprintf(serial, sizeof(serial), "%d", mac_addr);
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return serial;
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}
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/*
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* Set up "Over Current Control 1" (reg 0x58) on the first OHCI device.
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* The remaining ports on the second device are for mcpie2/sdcard and
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* can stay at the power-on default value.
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*
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* The schematic shows this transposed mapping for the first device:
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* chipset port 0 -> port 1 (j12 external 2, usboc0#)
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* chipset port 1 -> port 4 (j17 mpcie1)
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* chipset port 2 -> port 2 (j14 header row1, usboc1#)
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* chipset port 3 -> port 3 (j14 header row2, usboc1#)
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* chipset port 4 -> port 0 (j12 external 1. usboc0#)
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*
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* Register mapping:
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* bit0-3: Mapping for HS Port 0
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* bit4-7: Mapping for HS Port 1
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* bit8-11: Mapping for HS Port 2
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* bit12-15: Mapping for HS Port 3
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* bit16-19: Mapping for HS Port 4
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* bit20-31: Reserved (0)
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*
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* power-on default: 0xfffff
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* A value >7 will disable the overcurrent detection.
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*/
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static void usb_oc_setup(void)
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{
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device_t dev = dev_find_slot(0, PCI_DEVFN(0x12, 0));
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pci_write_config32(dev, 0x58, 0x011f0);
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}
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/*
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* We will stuff the memory size into the smbios sku location.
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*/
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const char *smbios_mainboard_sku(void)
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{
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static char sku[5];
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if (sku[0] != 0)
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return sku;
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if (!get_spd_offset())
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snprintf(sku, sizeof(sku), "2 GB");
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else
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snprintf(sku, sizeof(sku), "4 GB");
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return sku;
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}
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static void mainboard_final(void *chip_info)
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{
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u32 mmio_base;
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printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Final.\n");
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/*
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* LED1/D7/GPIO_189 should be 0
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* LED2/D6/GPIO_190 should be 1
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* LED3/D5/GPIO_191 should be 1
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*/
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mmio_base = find_gpio_base();
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configure_gpio(mmio_base, GPIO_189, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW);
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configure_gpio(mmio_base, GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH);
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configure_gpio(mmio_base, GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH);
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usb_oc_setup();
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}
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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.final = mainboard_final,
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};
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