f02bf35e00
The maximum ACPI table size is currently hardcoded to 144 KiB. When using QEMU with TPM enabled there is ~200 KiB of ACPI tables returned by the fw_cfg interface, so in order to allow this to be overridden by a mainboard move it to Kconfig. This is seen when using a TPM with qemu as it will hang when processing the fw_cfg tables. qemu-system-x86_64 \ -machine q35 -enable-kvm -vga virtio -serial stdio \ -drive 'id=hd,file=disk.bin' -bios coreboot.rom \ -chardev 'socket,id=swtpm,path=/tmp/swtpm/swtpm-sock' \ -tpmdev 'emulator,id=tpm0,chardev=swtpm' \ -device 'tpm-tis,tpmdev=tpm0' Change-Id: Ib5baa8fe12cb9027a340875f1ccf5fef6f9460bd Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
331 lines
7.8 KiB
Text
331 lines
7.8 KiB
Text
##
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## SPDX-License-Identifier: GPL-2.0-only
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## This file is part of the coreboot project.
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##
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config ARCH_X86
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bool
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select PCI
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select RELOCATABLE_MODULES
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# stage selectors for x86
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config ARCH_BOOTBLOCK_X86_32
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bool
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select ARCH_X86
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config ARCH_VERSTAGE_X86_32
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bool
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select ARCH_X86
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config ARCH_ROMSTAGE_X86_32
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bool
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select ARCH_X86
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config ARCH_POSTCAR_X86_32
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bool
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default ARCH_ROMSTAGE_X86_32 && POSTCAR_STAGE
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config ARCH_RAMSTAGE_X86_32
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bool
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select ARCH_X86
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# stage selectors for x64
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config ARCH_BOOTBLOCK_X86_64
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bool
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select ARCH_X86
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config ARCH_VERSTAGE_X86_64
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bool
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select ARCH_X86
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config ARCH_ROMSTAGE_X86_64
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bool
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select ARCH_X86
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config ARCH_POSTCAR_X86_64
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bool
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default ARCH_ROMSTAGE_X86_64 && POSTCAR_STAGE
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config ARCH_RAMSTAGE_X86_64
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bool
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select ARCH_X86
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if ARCH_X86
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config ARCH_X86_64_PGTBL_LOC
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hex "x86_64 page table location in CBFS"
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depends on ARCH_BOOTBLOCK_X86_64
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default 0xfffea000
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help
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The position where to place pagetables. Needs to be known at
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compile time. Must not overlap other files in CBFS.
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config USE_MARCH_586
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def_bool n
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help
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Allow a platform or processor to select to be compiled using
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the '-march=i586' option instead of the typical '-march=i686'
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# This is an SMP option. It relates to starting up APs.
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# It is usually set in mainboard/*/Kconfig.
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# TODO: Improve description.
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config AP_IN_SIPI_WAIT
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bool
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default n
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depends on ARCH_X86 && SMP
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config X86_RESET_VECTOR
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hex
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depends on ARCH_X86
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default 0xfffffff0
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help
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Specify the location of the x86 reset vector. In traditional devices
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this must match the architectural reset vector to produce a bootable
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image. Nontraditional designs may use this to position the reset
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vector into its desired location.
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config RESET_VECTOR_IN_RAM
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bool
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depends on ARCH_X86
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help
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Select this option if the x86 soc implements custom code to handle the
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reset vector in RAM instead of the traditional 0xfffffff0 location.
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# Aligns 16bit entry code in bootblock so that hyper-threading CPUs
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# can boot AP CPUs to enable their shared caches.
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config SIPI_VECTOR_IN_ROM
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bool
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default n
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depends on ARCH_X86
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# Set the rambase for systems that still need it, only 5 chipsets as of
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# Sep 2018. This value was 0x100000, chosen to match the entry point
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# of Linux 2.2 in 1999. The new value, 14 MiB, makes a lot more sense
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# for as long as we need it; with luck, that won't be much longer.
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# In the long term, both RAMBASE and RAMTOP should be removed.
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# This value leaves more than 1 MiB which is required for fam10
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# and broadwell_de.
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config RAMBASE
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hex
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default 0xe00000
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config RAMTOP
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hex
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default 0x1000000
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depends on ARCH_X86
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# Traditionally BIOS region on SPI flash boot media was memory mapped right below
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# 4G and it was the last region in the IFD. This way translation between CPU
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# address space to flash address was trivial. However some IFDs on newer SoCs
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# have BIOS region sandwiched between descriptor and other regions. Turning off
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# this option enables soc code to provide custom mmap_boot.c which can be used to
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# implement complex translation.
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config X86_TOP4G_BOOTMEDIA_MAP
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bool
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default y
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# This is something you almost certainly don't want to mess with.
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# How many SIPIs do we send when starting up APs and cores?
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# The answer in 2000 or so was '2'. Nowadays, on many systems,
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# it is 1. Set a safe default here, and you can override it
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# on reasonable platforms.
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config NUM_IPI_STARTS
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int
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default 2
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config CBMEM_TOP_BACKUP
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def_bool n
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help
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Platform implements non-volatile storage to cache cbmem_top()
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over stage transitions and optionally also over S3 suspend.
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config PRERAM_CBMEM_CONSOLE_SIZE
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hex
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default 0xc00
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help
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Increase this value if preram cbmem console is getting truncated
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config PC80_SYSTEM
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bool
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default y if ARCH_X86
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config BOOTBLOCK_DEBUG_SPINLOOP
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bool
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default n
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help
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Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait
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for a JTAG debugger to break into the execution sequence.
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config HAVE_CMOS_DEFAULT
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def_bool n
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depends on HAVE_OPTION_TABLE
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config CMOS_DEFAULT_FILE
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string
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default "src/mainboard/$(MAINBOARDDIR)/cmos.default"
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depends on HAVE_CMOS_DEFAULT
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config IOAPIC_INTERRUPTS_ON_FSB
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bool
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default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
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config IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
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bool
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default n
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config HPET_ADDRESS_OVERRIDE
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def_bool n
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config HPET_ADDRESS
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hex
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default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
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config ID_SECTION_OFFSET
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hex
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default 0x80
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# 64KiB default bootblock size
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config C_ENV_BOOTBLOCK_SIZE
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hex
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default 0x10000
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# Default address romstage is to be linked at
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config ROMSTAGE_ADDR
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hex
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default 0x2000000
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# Default address verstage is to be linked at
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config VERSTAGE_ADDR
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hex
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default 0x2000000
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# Use the post CAR infrastructure for tearing down cache-as-ram
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# from a program loaded in RAM and subsequently loading ramstage.
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config POSTCAR_STAGE
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def_bool y
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depends on ARCH_X86
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config VERSTAGE_DEBUG_SPINLOOP
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bool
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default n
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help
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Add a spin (JMP .) in assembly_entry.S during early verstage to wait
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for a JTAG debugger to break into the execution sequence.
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config ROMSTAGE_DEBUG_SPINLOOP
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bool
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default n
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help
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Add a spin (JMP .) in assembly_entry.S during early romstage to wait
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for a JTAG debugger to break into the execution sequence.
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choice
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prompt "Bootblock behaviour"
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default BOOTBLOCK_SIMPLE
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depends on !VBOOT
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config BOOTBLOCK_SIMPLE
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bool "Always load fallback"
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config BOOTBLOCK_NORMAL
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select CONFIGURABLE_CBFS_PREFIX
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bool "Switch to normal if CMOS says so"
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endchoice
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config SKIP_MAX_REBOOT_CNT_CLEAR
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bool "Do not clear reboot count after successful boot"
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depends on BOOTBLOCK_NORMAL
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help
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Do not clear the reboot count immediately after successful boot.
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Set to allow the payload to control normal/fallback image recovery.
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Note that it is the responsibility of the payload to reset the
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normal boot bit to 1 after each successful boot.
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config ACPI_NO_PCAT_8259
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bool
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help
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Selected by platforms that don't expose a PC/AT 8259 PIC pair.
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config ACPI_HAVE_PCAT_8259
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def_bool y if !ACPI_NO_PCAT_8259
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config ACPI_CPU_STRING
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string
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default "\\_SB.CP%02d"
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depends on HAVE_ACPI_TABLES
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help
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Sets the ACPI name string in the processor scope as written by
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the acpigen function. Default is \_SB.CPxx. Note that you need
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the \ escape character in the string.
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config COLLECT_TIMESTAMPS_NO_TSC
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bool
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default n
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depends on COLLECT_TIMESTAMPS
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help
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Use a non-TSC platform-dependent source for timestamps.
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config COLLECT_TIMESTAMPS_TSC
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bool
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default y if !COLLECT_TIMESTAMPS_NO_TSC
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default n
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depends on COLLECT_TIMESTAMPS
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help
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Use the TSC as the timestamp source.
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config PAGING_IN_CACHE_AS_RAM
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bool
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default n
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depends on ARCH_X86
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help
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Chipsets scan select this option to preallocate area in cache-as-ram
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for storing paging data structures. PAE paging is currently the
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only thing being supported.
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config NUM_CAR_PAGE_TABLE_PAGES
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int
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default 5
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depends on PAGING_IN_CACHE_AS_RAM
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help
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The number of 4KiB pages that should be pre-allocated for page tables.
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# Provide the interrupt handlers to every stage. Not all
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# stages may take advantage.
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config IDT_IN_EVERY_STAGE
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bool
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default n
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depends on ARCH_X86
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config HAVE_CF9_RESET
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bool
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config HAVE_CF9_RESET_PREPARE
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bool
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depends on HAVE_CF9_RESET
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config PIRQ_ROUTE
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bool
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default n
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config MAX_PIRQ_LINKS
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int
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default 4
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depends on PIRQ_ROUTE
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help
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This variable specifies the number of PIRQ interrupt links which are
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routable. On most chipsets, this is 4, INTA through INTD. Some
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chipsets offer more than four links, commonly up to INTH. They may
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also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
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table specifies links greater than 4, pirq_route_irqs will not
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function properly, unless this variable is correctly set.
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config MAX_ACPI_TABLE_SIZE_KB
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int
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default 144
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help
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Set the maximum size of all ACPI tables in KiB.
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endif
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