a2b7bd859a
Once the PCI command register is written the bridge forwards
future IO and memory regions, as programmed in the respective base
and limit registers, to the secondary PCI bus.
Since the LPC function claims the resources for IOAPIC, ROM and
low IO (0x0-0xfff) in its read_resources() call, the PCI-to-PCI
configuration will not overlap those regions and does not hide
the resources mentioned in the original comment.
The bridge was disable in the following commit [1]
commit a8e1168064
Author: Stefan Reinauer <stepan@coresystems.de>
Date: Wed Mar 11 14:54:18 2009 +0000
This patch contains some significant updates to the i82801gx component and will
be required for a series of later patches. Roughly it contains:
but unfortunately it was not noted which system this caused
problems with.
[1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=a8e1168064b34b46494b58480411a11bc98340f6
Change-Id: I75128d83a344f4a0e09a3ea623c7f92a016ebfb9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/2706
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
140 lines
4 KiB
C
140 lines
4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include "i82801gx.h"
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static void pci_init(struct device *dev)
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{
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u16 reg16;
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u8 reg8;
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/* Enable Bus Master */
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reg16 = pci_read_config16(dev, PCI_COMMAND);
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reg16 |= PCI_COMMAND_MASTER;
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pci_write_config16(dev, PCI_COMMAND, reg16);
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/* This device has no interrupt */
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pci_write_config8(dev, INTR, 0xff);
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/* disable parity error response and SERR */
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reg16 = pci_read_config16(dev, BCTRL);
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reg16 &= ~(1 << 0);
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reg16 &= ~(1 << 1);
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pci_write_config16(dev, BCTRL, reg16);
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/* Master Latency Count must be set to 0x04! */
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reg8 = pci_read_config8(dev, SMLT);
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reg8 &= 0x07;
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reg8 |= (0x04 << 3);
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pci_write_config8(dev, SMLT, reg8);
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/* Will this improve throughput of bus masters? */
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pci_write_config8(dev, PCI_MIN_GNT, 0x06);
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/* Clear errors in status registers */
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reg16 = pci_read_config16(dev, PSTS);
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//reg16 |= 0xf900;
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pci_write_config16(dev, PSTS, reg16);
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reg16 = pci_read_config16(dev, SECSTS);
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// reg16 |= 0xf900;
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pci_write_config16(dev, SECSTS, reg16);
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}
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static void ich_pci_dev_enable_resources(struct device *dev)
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{
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const struct pci_operations *ops;
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uint16_t command;
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/* Set the subsystem vendor and device id for mainboard devices */
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ops = ops_pci(dev);
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if (dev->on_mainboard && ops && ops->set_subsystem) {
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printk(BIOS_DEBUG, "%s subsystem <- %04x/%04x\n",
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dev_path(dev), dev->subsystem_vendor,
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dev->subsystem_device);
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ops->set_subsystem(dev, dev->subsystem_vendor,
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dev->subsystem_device);
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}
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command = pci_read_config16(dev, PCI_COMMAND);
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command |= dev->command;
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printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
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pci_write_config16(dev, PCI_COMMAND, command);
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}
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static void ich_pci_bus_enable_resources(struct device *dev)
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{
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uint16_t ctrl;
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/* enable IO in command register if there is VGA card
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* connected with (even it does not claim IO resource)
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*/
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if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA)
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dev->command |= PCI_COMMAND_IO;
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ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
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ctrl |= dev->link_list->bridge_ctrl;
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ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
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printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
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pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
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/* This is the reason we need our own pci_bus_enable_resources */
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ich_pci_dev_enable_resources(dev);
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}
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static void set_subsystem(device_t dev, unsigned int vendor,
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unsigned int device)
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{
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/* NOTE: This is not the default position! */
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if (!vendor || !device) {
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pci_write_config32(dev, 0x54,
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pci_read_config32(dev, PCI_VENDOR_ID));
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} else {
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pci_write_config32(dev, 0x54,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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}
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static struct pci_operations pci_ops = {
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.set_subsystem = set_subsystem,
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};
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static struct device_operations device_ops = {
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.read_resources = pci_bus_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = ich_pci_bus_enable_resources,
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.init = pci_init,
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.scan_bus = pci_scan_bridge,
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.ops_pci = &pci_ops,
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};
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/* Desktop */
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/* 82801BA/CA/DB/EB/ER/FB/FR/FW/FRW/GB/GR/GDH/HB/IB/6300ESB/i3100 */
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static const struct pci_driver i82801g_pci __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = 0x244e,
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};
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/* Mobile / Ultra Mobile */
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/* 82801BAM/CAM/DBL/DBM/FBM/GBM/GHM/GU/HBM/HEM */
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static const struct pci_driver i82801gmu_pci __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = 0x2448,
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};
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