1c6d919eb0
This patch adds the 10ms TRSTRCY delay between a reset and the following Set Address command that is required by the USB 2.0 specification to the EHCI root hub driver. The generic_hub driver that's used for XHCI and external hubs already included this delay. This is such a glaring violation of the spec that I'm really amazed how many USB 2.0 devices we tested before seemed perfectly fine with responding to a Set Address within 2 microframes of the reset... It also increases the port reset hold delay by one millisecond to avoid an ugly race condition on Tegra SoCs: they decided to time the 50ms themselves instead of relying on the CPU to do it (fair enough), and to automatically transition Port Reset to 0 and Port Enable to 1 after that (bad idea). If the CPU's read-modify-write to clear Port Reset races exactly with the host controller setting Port Enable, we may end up clearing the bit again and going into the companion controller handoff path later on. The added millisecond shouldn't cause any problems for other host controllers and is not a big deal compared to other delays in this code path. BUG=chrome-os-partner:26749 TEST=Run several dozen reboot loops with The USB Stick of Death (TM) (a blue Patriot XT 13fe:5200 with bcdDevice = 1.00), make sure it always gets detected correctly. Original-Change-Id: Idd3329ae6d7e5e1c07a84a5475549b3459836b31 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/189872 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Reviewed-by: Jim Lin <jilin@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 4deca38e9d79f6373f4418fcaf51a6945232c8b8) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I68a29bfd2e0f30409fbfc330b2575f0f9f61a79d Reviewed-on: http://review.coreboot.org/7221 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> |
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.. | ||
arch | ||
bin | ||
configs | ||
crypto | ||
curses | ||
drivers | ||
include | ||
libc | ||
libcbfs | ||
liblzma | ||
libpci | ||
sample | ||
tests | ||
util | ||
Config.in | ||
Doxyfile | ||
LICENSES | ||
Makefile | ||
Makefile.inc | ||
README |
README
------------------------------------------------------------------------------- libpayload README ------------------------------------------------------------------------------- libpayload is a minimal library to support standalone payloads that can be booted with firmware like coreboot. It handles the setup code, and provides common C library symbols such as malloc() and printf(). Note: This is _not_ a standard library for use with an operating system, rather it's only useful for coreboot payload development! See http://coreboot.org for details on coreboot. Installation ------------ $ git clone http://review.coreboot.org/p/coreboot.git $ cd coreboot/payloads/libpayload $ make menuconfig $ make $ sudo make install (optional, will install into /opt per default) As libpayload is for 32bit x86 systems only, you might have to install the 32bit libgcc version, otherwise your payloads will fail to compile. On Debian systems you'd do 'apt-get install gcc-multilib' for example. Usage ----- Here's an example of a very simple payload (hello.c) and how to build it: #include <libpayload.h> int main(void) { printf("Hello, world!\n"); return 0; } Building the payload using the 'lpgcc' compiler wrapper: $ lpgcc -o hello.elf hello.c Please see the sample/ directory for details. Website and Mailing List ------------------------ The main website is http://www.coreboot.org/Libpayload. For additional information, patches, and discussions, please join the coreboot mailing list at http://coreboot.org/Mailinglist, where most libpayload developers are subscribed. Copyright and License --------------------- See LICENSES.